C505_9708 SIEMENS [Siemens Semiconductor Group], C505_9708 Datasheet - Page 227
C505_9708
Manufacturer Part Number
C505_9708
Description
8-Bit CMOS Microcontroller
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
1.C505_9708.pdf
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U
Semiconductor Group
TH1. . . . . . . . . . . . . . . . . . . 3-13, 3-15, 6-16
TH2. . . . . . . . . . . . . . . . . . . 3-13, 3-16, 6-27
TI . . . . . . . . . . . . . . . 3-15, 6-44, 6-45, 7-11
Timer/counter . . . . . . . . . . . . . . . . . . . . 6-15
Timings
TL0 . . . . . . . . . . . . . . . . . . . 3-13, 3-15, 6-16
TL1 . . . . . . . . . . . . . . . . . . . 3-13, 3-15, 6-16
TL2 . . . . . . . . . . . . . . . . . . . 3-13, 3-16, 6-27
TMOD. . . . . . . . . . . . . . . . . 3-13, 3-15, 6-18
TR0. . . . . . . . . . . . . . . . . . . . . . . 3-15, 6-17
TR1. . . . . . . . . . . . . . . . . . . . . . . 3-15, 6-17
TSEG1 . . . . . . . . . . . . . . . . . . . . 3-18, 6-71
TSEG2 . . . . . . . . . . . . . . . . . . . . 3-18, 6-71
TxD. . . . . . . . . . . . . . . . . . . . . . . 3-16, 6-43
TXDC . . . . . . . . . . . . . . . . . . . . . 3-17, 6-97
TXIE . . . . . . . . . . . . . . . . . . . . . . 3-18, 6-76
TXOK . . . . . . . . . . . . . . . . . . . . . 3-18, 6-68
TXRQ . . . . . . . . . . . . . . . . . . . . . 3-18, 6-77
UAR0 . . . . . . . . . . . . . . . . . 3-14, 3-18, 6-79
UAR1 . . . . . . . . . . . . . . . . . 3-14, 3-18, 6-79
UGML0 . . . . . . . . . . . . . . . . 3-14, 3-18, 6-73
UGML1 . . . . . . . . . . . . . . . . 3-14, 3-18, 6-73
UMLM0. . . . . . . . . . . . . . . . 3-14, 3-18, 6-74
Timer/counter 0 and 1. . . . . . 6-15 to 6-22
Timer/counter 2. . . . . . . . . . . 6-23 to 6-42
Data memory read cycle. . . . . . . . . 10-14
Data memory write cycle . . . . . . . . 10-15
External clock timing. . . . . . . . . . . . 10-15
Program memory read cycle. . . . . . 10-13
ROM verification mode 1 . . . . . . . . 10-16
ROM verification mode 2 . . . . . . . . 10-17
Mode 0, 13-bit timer/counter . . . . . 6-19
Mode 1, 16-bit timer/counter . . . . . 6-20
Mode 2, 8-bit rel. timer/counter . . . 6-21
Mode 3, two 8-bit timer/counter. . . 6-22
Registers . . . . . . . . . . . . . . 6-16 to 6-18
Block diagram . . . . . . . . . . . . . . . . 6-24
Capture function . . . . . . . . 6-40 to 6-42
Compare function . . . . . . . 6-32 to 6-37
Compare mode 0 . . . . . . . 6-32 to 6-35
Compare mode 1 . . . . . . . 6-36 to 6-37
Compare mode interrupts . . . . . . . 6-38
General operation . . . . . . . . . . . . . 6-30
Port functions . . . . . . . . . . . . . . . . 6-23
Registers . . . . . . . . . . . . . . 6-25 to 6-29
Reload configuration . . . . . . . . . . . 6-31
11-5
V
W
X
UMLM1 . . . . . . . . . . . . . . . 3-14, 3-18, 6-74
Unprotected ROM verify timing . . . . . . 4-10
Version registers . . . . . . . . . . . . . . . . . 4-13
VR0 . . . . . . . . . . . . . . . . . . 3-12, 3-17, 4-13
VR1 . . . . . . . . . . . . . . . . . . 3-12, 3-17, 4-13
VR2 . . . . . . . . . . . . . . . . . . 3-12, 3-17, 4-13
Watchdog timer . . . . . . . . . . . . . . 8-1 to 8-5
WDT. . . . . . . . . . . . . . . . . . . . . . . 3-15, 8-3
WDTPSEL . . . . . . . . . . . . . . . . . . 3-15, 8-2
WDTREL . . . . . . . . . . . . . . . 3-13, 3-15, 8-2
WDTS . . . . . . . . . . . . . . . . . . . . . 3-15, 8-3
WR. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
WS . . . . . . . . . . . . . . . . . . . . . . . . 3-15, 9-2
XMAP0. . . . . . . . . . . . . . . . . . . . . 3-3, 3-16
XMAP1. . . . . . . . . . . . . . . . . . . . . 3-3, 3-16
XPAGE . . . . . . . . . . . . . . . . 3-5, 3-12, 3-15
XRAM operation . . . . . . . . . . . . . . . . . . 3-3
XTD . . . . . . . . . . . . . . . . . . 3-18, 6-61, 6-80
Block diagram . . . . . . . . . . . . . . . . . . 8-1
Control/status flags . . . . . . . . . . . . . . 8-3
Input clock selection. . . . . . . . . . . . . . 8-2
Refreshing of the WDT. . . . . . . . . . . . 8-5
Reset operation . . . . . . . . . . . . . . . . . 8-5
Starting of the WDT . . . . . . . . . . . . . . 8-4
Time-out periods . . . . . . . . . . . . . . . . 8-2
Access control . . . . . . . . . . . . . . . . . . 3-3
Accessing through DPTR. . . . . . . . . . 3-5
Accessing through R0/R1 . . . . . . . . . 3-5
Behaviour of P2/P0 . . . . . . . . . . . . . . 3-9
Reset operation . . . . . . . . . . . . . . . . . 3-9
Table - P0/P2 during MOVX instr. . . 3-10
XPAGE register . . . . . . . . . . . . . . . . . 3-5
Use of P2 as I/O port . . . . . . . . . . . 3-8
Write page address to P2 . . . . . . . . 3-6
Write page address to XPAGE . . . . 3-7
C505 / C505C
1997-08-01
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