C505_9708 SIEMENS [Siemens Semiconductor Group], C505_9708 Datasheet - Page 191

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C505_9708

Manufacturer Part Number
C505_9708
Description
8-Bit CMOS Microcontroller
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
8.1.2 Watchdog Timer Control / Status Flags
The watchdog timer is controlled by two control flags (located in SFR IEN0 and IEN1) and one
status flag (located in SFR IP0).
Special Function Register IEN0 (Address A8 H )
Special Function Register IEN1 (Address B8 H )
Special Function Register IP0 (Address A9 H )
Bit
WDT
SWDT
WDTS
Immediately after start, the Watchdog Timer is initialized to the reload value programmed in
WDTREL.0-WDTREL.6. After an external HW reset, an oscillator watchdog power on reset, or a
watchdog timer reset, register WDTREL is cleared to 00 H . The lower seven bits of WDTREL can be
loaded by software at any time.
Semiconductor Group
Bit No.
A9 H
A8 H
B8 H
EXEN2 SWDT
OWDS WDTS
MSB
EAL
AF
BF
7
H
H
The shaded bits are not used for fail save control.
WDT
AE
BE
6
H
H
Function
Watchdog timer refresh flag.
Set to initiate a refresh of the watchdog timer. Must be set directly
before SWDT is set to prevent an unintentional refresh of the
watchdog timer.
Watchdog timer start flag.
Set to activate the Watchdog Timer. When directly set after setting
WDT, a watchdog timer refresh is performed.
Watchdog timer status flag.
Set by hardware when a watchdog Timer reset occured. Can be
cleared and set by software.
IP0.5
EX6
ET2
AD
BD
5
H
H
IP0.4
EX5
ES
AC
BC
4
H
H
8-3
IP0.3
ET1
EX4
AB
BB
3
H
H
IP0.2
EX1
EX3
AA
BA
2
H
H
ECAN EADC
IP0.1
ET0
A9
B9
1
Fail Save Mechanisms
H
H
IP0.0
LSB
EX0
A8
B8
0
H
H
Reset Value : 00 H
Reset Value : 00 H
Reset Value : 00 H
C505 / C505C
IEN0
IEN1
IP0
1997-08-01

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