C505_9708 SIEMENS [Siemens Semiconductor Group], C505_9708 Datasheet - Page 51

• Manufacturer Part Number: C505_9708
• Description: 8-Bit CMOS Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

4.7.2 Protected ROM Mode
If the ROM is protected, the ROM verification mode 2 as shown in figure 4-5 is used to verify the
contents of the ROM. The detailed timing characteristics of the ROM verification mode is shown in
the AC specifications (chapter 10).
Figure 4-5
ROM Verification Mode 2
ROM verification mode 2 is selected if the inputs PSEN, EA, and ALE are put to the specified logic
levels. With RESET going inactive, the ROM verification mode 2 sequence is started. The C505
outputs an ALE signal with a period of 3 CLP and expects data bytes at port 0. The data bytes at port
0 are assigned to the ROM addresses in the following way :
The C505-2R does not output any address information during the ROM verification mode 2. The
first data byte to be verified is always the byte which is assigned to the internal ROM address 0000 H
and must be put onto the data bus with the falling edge of RESET. With each following ALE pulse
the ROM address pointer is internally incremented and the expected data byte for the next ROM
address must be delivered externally.
Between two ALE pulses the data at port 0 is latched (at 3 CLP after ALE rising edge) and compared
internally with the ROM content of the actual address. If an verify error is detected, the error
Semiconductor Group
RESET
ALE
Port 0
P3.5
1. Data Byte =
2. Data Byte =
3. Data Byte =
16. Data Byte =
:
:
Inputs : ALE =
1. ALE pulse
after reset
PSEN, EA =
RESET =
V
content of internal ROM address 0000 H
content of internal ROM address 0001 H
content of internal ROM address 0002 H
content of internal ROM address 000FH
SS
V
3 CLP
IH
Data for Addr. 0
6 CLP
Latch
4-11
Data for
Addr. 1
Latch
Data for Ad.
X 16 - 1
Data for Addr. X 16
Low: Verify Error High: Verify ok
External Bus Interface
Latch
C505 / C505C
Data for Addr.
X 16 + 1
Latch
MCT03289
1997-08-01