C505_9708 SIEMENS [Siemens Semiconductor Group], C505_9708 Datasheet - Page 169

• Manufacturer Part Number: C505_9708
• Description: 8-Bit CMOS Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Depending on the selected prescaler ratio (see figure 6-43), two different relationships between
machine cycles and A/D conversion are possible. The A/D conversion is always started with the
beginning of a processor cycle when it has been started by writing SFR ADST with dummy data.
The ADST write operation may take one or two machine cycles. In figure 6-45, the instruction
MOV ADST,#0 starts the A/D conversion (machine cycles X-1 and X). The total A/D conversion
(sample and conversion phase) is finished with the end of the 10th ADC clock cycle after the A/D
conversion start. The actual machine number of machine cycles needed follows the table in
Figure 6-44. In the next machine cycle the conversion result is written into the ADDAT register and
can be read in the same cycle by an instruction (e.g. MOV A,ADDAT). If continuous conversion is
selected (bit ADM set), the next conversion is started with the beginning of the machine cycle which
follows the write result cycle.
The BSY bit is set at the beginning of the first A/D conversion machine cycle and reset at the
beginning of the write result cycle. If continuous conversion is selected, BSY is again set with the
beginning of the machine cycle which follows the write result cycle. This means that in continuous
conversion mode BSY is not set for a complete machine cycle. Therefore, in continuous conversion
mode it is not recommended to poll the BSY bit using for e.g. the JNB instruction.
The interrupt flag IADC is set at the end of the A/D conversion so that it is polled the first time in
S1P2 of the machine cycle following the completion of conversion. If the A/D converter interrupt is
enabled and the A/D converter interrupt is prioritized to be serviced immediately, the first instruction
of the interrupt service routine will be executed in the fourth machine cycle which follows the write
result cycle. The IADC bit must be reset by software.
Depending on the application, typically there are three methods to handle the A/D conversion in the
C505.
Semiconductor Group
– Software delay
– Polling BSY bit,
– A/D conversion interrupt
The machine cycles during an A/D conversion are counted and the program executes a
software delay (e.g. NOPs) before reading the A/D conversion result in the write result cycle.
The end of conversion is indicated by the IADC flag.
The BSY bit is polled and the program waits until BSY=0. Attention : a polling JB which is two
machine cycles long, possibly may not recognize the BSY=0 condition during the write result
cycle in the continuous conversion mode.
After the start of an A/D conversion the A/D converter interrupt is enabled. The result of the
A/D conversion is read in the interrupt service routine. If other C505 interrupts are enabled,
the interrupt latency must be regarded. Therefore, this software method is the slowest method
to get the result of an A/D conversion.
6-107
On-Chip Peripheral Components
C505 / C505C
1997-08-01