C505_9708 SIEMENS [Siemens Semiconductor Group], C505_9708 Datasheet - Page 52

• Manufacturer Part Number: C505_9708
• Description: 8-Bit CMOS Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

condition is stored internally. After each 16th data byte the cumulated verify result (pass or fail) of
the last 16 verify operations is output at P3.5. This means that P3.5 stays at static level (low for fail
and high for pass) during the time when the following 16 bytes are checked. In ROM verification
mode 2, the C505 must be provided with a system clock at the XTAL pins.
Figure 4-6 shows an application example of an external circuitry which allows to verify a protected
ROM inside the C505-2R in ROM verification mode 2. With RESET going inactive, the C505-2R
starts the ROM verify sequence. Its ALE is clocking a 14-bit address counter. This counter
generates the addresses for an external EPROM which is programmed with the contents of the
internal (protected) ROM. The verify detect logic typically displays the pass/fail information of the
verify operation. P3.5 can be latched with the falling edge of ALE.
When the last byte of the internal ROM has been handled, the C505-2R starts generating a PSEN
signal. This signal or the CY signal of the address counter indicate to the verify detect logic the end
of the internal ROM verification.
Figure 4-6
ROM Verification Mode 2 - External Circuitry Example
Semiconductor Group
C505-2R
RESET
Port 0
PSEN
P3.5
ALE
EA
V
2K
CC
&
&
CLK
4-12
Address
Counter
14 - Bit
Carry
S
V
CC
Detect
Verify
Logic
External Bus Interface
A0 - A13
D0 - D7
CS
Campare
Code
ROM
MCS03290
OE
C505 / C505C
1997-08-01