Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 122

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

DREQ0
Phi
Memory to I/O (Memory Mapped I/O) — Channel 0
For memory to/from I/O (and memory to/from memory mapped I/O) the
DREQ0 input is used to time the DMA transfers. In addition, the TEND0
(Transfer End) output is used to indicate the last (byte count register
BCR0 =
The DREQ0 input can be programmed as level- or edge-sensitive.
When level-sense is programmed, the DMA operation begins when
DREQ0 is sampled Low. If DREQ0 is sampled High, after the next DMA
byte transfer, control is relinquished to the Z8X180 CPU. As illustrated in
Figure 47, DREQ0 is sampled at the rising edge of the clock cycle prior to
T3, (that is, either T2 or Tw).
Figure 47.
When edge-sense is programmed, DMA operation begins at the falling
edge of DREQ0 If another falling edge is detected before the rising edge
of the clock prior to T3 during DMA write cycle (that is T2 or Tw), the
DMAC continues operating. If an edge is not detected, the CPU is given
control after the current byte DMA transfer completes. The CPU
continues operating until a DREQ0 falling edge is detected before the
Tw
DMA
Write
Cycle
Tw
**
00H
T3
CPU Operation and DMA Operation DREQ0 is Programmed
for Level-Sense
T1 T2
) transfer.
CPU
Machine
Cycle
**
T3
T1
DMA
Read
Cycle
T2
T3
T1
** DREQ0 is sampled at
T2
DMA
Write
Cycle (I/O)
Tw Tw
**
M PU Us e r M anual
T3
UM005001-ZMP0400
Z 8018x Fam il y
T1
T2
107