Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 86

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

A0
D0
MREQ
–
–
A19
WR
Phi
RD
D7
MI
stacked PC-1. If UFO is
equal to the stacked PC-2.
Bus Release cycle, Refresh cycle, DMA cycle, and WAIT cycle cannot be
inserted just after TTP state which is inserted for TRAP interrupt
sequence. Figure depicts TRAP Timing - 2nd Op Code undefined and
Figure illustrates Trap Timing - 3rd Op Code undefined.
Figure 32.
T1
2nd Op Code
Fetch Cycle
T2
Undefined
Op Code
T3
TRAP Timing Diagram -2nd Op Code Undefined
PC
Ti
Ti
Ti
1
, the starting address of the invalid instruction is
Ti
Ti
T1
T2
SP-1
PCH
PC Stacking
T3 T1
T2
SP-2
M PU Us e r M anual
PCL
UM005001-ZMP0400
T3
Z 8018x Fam il y
Restart from 0000H
T1
Op Code
Fetch Cycle
T2 T3
0000H
71