Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 167

no-image

Z8L180

Manufacturer Part Number
Z8L180
Description
Z8018x Family MPU
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z8L18020FSC
Manufacturer:
Zilog
Quantity:
10 000
Part Number:
Z8L18020FSC00TR
Manufacturer:
Zilog
Quantity:
10 000
Part Number:
Z8L18020FSG
Manufacturer:
IR
Quantity:
101
Part Number:
Z8L18020FSG
Manufacturer:
Zilog
Quantity:
10 000
Part Number:
Z8L18020VSC
Manufacturer:
NXP
Quantity:
1 302
Part Number:
Z8L18020VSC
Manufacturer:
Zilog
Quantity:
10 000
Part Number:
Z8L18020VSC00TR
Manufacturer:
Zilog
Quantity:
10 000
152
UM005001-ZMP0400
Z 8018x Fam il y
M PU Us e r M anual
CSI/O Operation Timing Notes
CSI/O Operation Notes
c. Poll the RE bit in CNTR until RE =
d. Read the receive data from TRDR.
e. Repeat steps 2 to 4 for each receive data byte.
Receive–Interrupts
a. Poll the RE bit in CNTR until RE is
b. Set the RE and EIE bits in CNTR to
c. When the receive interrupt occurs read the receive data from
d. Set the RE bit in CNTR to
e. Repeat steps 3 and 4 for each receive data byte.
Transmitter clocking and receiver sampling timings are different from
internal and external clocking modes. Figure 59 to Figure 62 illustrate
CSI/O Transmit/Receive Timing.
The transmitter and receiver is disabled TE and RE
initializing or changing the baud rate.
Disable the transmitter and receiver (TE and RE =
initializing or changing the baud rate. When changing the baud rate
after completion of transmission or reception, a delay of at least one
bit time is required before baud rate modification.
When RE or TE is cleared to
or transmit operation is immediately terminated. Normally, TE or RE
is only cleared to
Simultaneous transmission and reception is not possible. Thus, TE
and RE are not both
TRDR.
0
when EF is
1
at the same time.
0
1
by software, a corresponding receive
1
.
.
0
0
1
.
.
.
0
= 0
) before
) when

Related parts for Z8L180