Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 95

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

80
UM005001-ZMP0400
A0
D0
MREQ
IORQ
Z 8018x Fam il y
M PU Us e r M anual
–
INT0
–
A19
WR
Phi
RD
M1
D7
ST
Last MC
Figure 40.
INT1, INT2
The operation of external interrupts INT1 and INT2 is a vector mode
similar to INT0 Mode 2. The difference is that INT1 and INT2 generate
the low-order byte of vector table address using the IL (Interrupt Vector
Low) register rather than fetching it from the data bus. This difference is
T1
T2
Vector Lower
Address Read
TW*
Lower Vector
TW*
INT0 Interrupt Mode 2 Timing Diagram
PC
T3
Ti
T1
PC is pushed onto stack
INT0 Acknowledge Cycle
T2 T3
SP-1
PCH
T1
T2
*Two Wait States are automatically inserted
SP-2
PCL
T3
Starting Address
(Lower Address)
T1
T2 T3
Vector
Interrupt
Manipulation
Cycle
T1
Vector+1
T2
Starting Address
(Upper Address)
Starting address
T1
Op Code
Fetch Cycle
T2
T3