Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 158

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

PS
1
Prescaler
Divide
Ratio
30
Baud Rate Generator
DR Rate
0
1
Sampling
Rate
16
64
Table 19. ASCI Baud Rate Selection (Continued)
The Z8S180/Z8L180 Baud Rate Generator (BRG) features two modes.
The first is the same as in the Z80180. The second is a 16-bit down
counter that divides the processor clock by the value in a 16-bit time
constant register, and is identical to the DMSCC BRG. This feature
SS2 SS1 SS0 Divide
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
(Z8S180/Z8L180-Class Processors Only)
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Baud Rate
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Ratio
16
32
64
—
16
32
64
—
1
2
4
8
1
2
4
8
General
Divide
Ratio
122880
fc
fc
15360
30720
15360
30720
61440
1920
3840
7680
1920
3840
7680
480
960
16
64
MHz
= 6.144
Baud Rate (Example)
—
—
MHz
(BPS)
= 4.608
9600
4800
2400
1200
2400
1200
37.5
600
300
150
600
300
150
—
75
—
MHz
M PU Us e r M anual
= 3.072
UM005001-ZMP0400
Z 8018x Fam il y
—
—
I/O
0
0
I
I
CKA
Clock
Frequency
60
120
240
480
960
1920
fc
60
120
240
480
960
1920
fc
30
30
143