Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 44

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

Bit
Figure 19.
The number of Wait States (TW) inserted in a specific cycle is the
maximum of the number requested by the WAIT input, and the number
automatically generated by the on-chip Wait State generator.
Bit 7, 6: MWI1 MWI0, (Memory Wait Insertion)
For CPU and DMAC cycles which access memory (including memory
mapped I/O), zero to three Wait States may be automatically inserted
depending on the programmed value in MWI1 and MWI0 as depicted in
Table 3
Table 3.
Bit 5, 4: IWI1, IWI0 (I/O Wait Insertion)
For CPU and DMA cycles which access external I/O (and interrupt
acknowledge cycles), one to six Wait States (TW) may be automatically
MW11
MWI1
R/W
0
0
1
1
7
Memory Wait States
MWI0
Control Register)
MWI0
R/W
Memory and I/O Wait State Insertion (DCNTL – DMA/Wait
6
0
1
0
1
MWI1
The Number of Wait States
R/W
5
MWI0
R/W
4
0
1
2
3
M PU Us e r M anual
UM005001-ZMP0400
Z 8018x Fam il y
29