Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 99

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

84
UM005001-ZMP0400
Z 8018x Fam il y
M PU Us e r M anual
Note: RETI machine cycles 9 and 10 not shown.
A0
M1 (M1E = 1)
M1 (M1E = 0)
–
A18 (A19)
Return from Subroutine (RETI) Instruction Sequence
When the
the RETI instruction sequence. The Z8X180 then refetches the RETI
instruction with four T-states in the
peripherals time to decode that cycle (See Figure 42). This procedure
allows the internal interrupt structure of the peripheral to properly decode
the instruction and behave accordingly.
The M1E bit of the Operation Mode Control Register (OMCR) must be
set to
instruction sequence. This condition is the desired operation when Z80
peripherals are connected to the Z8018X.
Figure 42.
The RETI instruction takes 22 T-states and 10 machine cycles. Table 10
lists the conditions of all the control signals during this sequence for the
D0
MREQ
–
Phi
RD
D7
ST
0
so that M1 signal is active only during the refetch of the RETI
EDH
T1
RETI Instruction Sequence
T2
/
4DH
PC
EDH
T3 T1
sequence is fetched by the Z8X180, it is recognized as
T2
4DH
T3
PC + 1
Ti
EDH
Ti
Ti
cycle allowing the Z80
T1
T2
EDH
PC
T3 Ti
T1
T2
PC + 1
4DH
T3
T1