Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 310

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

294
UM005001-ZMP0400
Register
ASCI Control Register B
Channel 0:
ASCI Control Register B
Channel 1:
Z8018x Family
MPU User Manual
Table 57. Internal I/O Registers (Continued)
CNTLB0
CNTLB1
Mnemonics Address
0
0
2
3
during RESET
* CTS: Depending on the condition 0f CTS Pin.
during RESET
PS: Cleared to 0.
R/W
divide ratio
bit
R/W
General
bit
SS2 1 0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
MPBT
invalid
R/W
invalid
MPBT
R/W
DR=0 (X 16)
Multi Processor Bit Transmit
External clock (frequency <
Multi Processor Bit Transmit
R/W
10240
MP
2560
1280
5120
(divide ratio=10)
0
R/W
320
160
MP
0
640
Multi Processor
Multi Processor
PS=0
R/W
CTS/
PS
Remarks
*
R/W
CTS/
PS
DR=1 (X 64)
0
Clear to send/Prescale
Clear to Send/Prescale
R/W
PEO
10240
20480
40960
0
PEO
R/W
2560
5120
1280
640
0
Parity Even or Odd
Parity Even or Odd
R/W
40)
DR
0
R/W
DR
DR=0 (X 16)
0
Divide Ratio
Divide Ratio
R/W
SS2
(divide ratio=30)
30720
15360
1
SS2
3840
7680
R/W
1920
480
1
960
PS=1
SS1
R/W
SS1
1
R/W
DR=1 (X 64)
1
Clock Source and
Speed Select
Clock Source and
Speed Select
R/W
SS0
122880
1
15360
30720
61440
SS0
1920
R/W
7680
3840
1