Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 182

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

BUSREQ
BUSACK
MREQ
IORQ
Phi
M1
Phi
E
E
NOTE : MC = Machine Cycle
Figure 67.
Figure 68.
Fetch Cycle
T1 T2 T3
Op Code
state
Last
Memory Read/
T1
Write Cycle
E Clock Timing Diagram (During Read/Write Cycle and
Interrupt Acknowledge Cycle
E Clock Timing in BUS RELEASE Mode
T2
TX
T3
T1
TX
I/O Read Cycle
T2
E
Tw
BUS RELEASE mode
E
T3
E
T1
I/O Write Cycle
T2
* Two wait states are automatically inserted
T3
NMI
Acknowledge
1st MC
T1
TX TX
T2
M PU Us e r M anual
UM005001-ZMP0400
T3
Z 8018x Fam il y
T1
INT0 Acknowledge
1st MC
T2
Tw*
Tw*
T3
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