Z8L180 ZILOG [Zilog, Inc.], Z8L180 Datasheet - Page 37

• Manufacturer Part Number: Z8L180
• Description: Z8018x Family MPU
• Manufacturer: ZILOG [Zilog, Inc.]

22
UM005001-ZMP0400
MREQ
Z 8018x Fam il y
M PU Us e r M anual
A0
WAIT
WR
RD
D0
Phi
–
–
A19
D7
T1
Figure 12.
I/O Read/Write Timing
I/O Read/Write operations differ from memory Read/Write operations in
the following three ways:
•
•
•
At least one Wait State (TW) is always inserted for I/O read and write
cycles (except internal I/O cycles).
Figure 13 illustrates I/O read/write timing with the automatically inserted
Wait State (TW).
The IORQ (I/O Request) signal is asserted Low instead of the MREQ
signal
The 16-bit I/O address is not translated by the MMU
A16–A19 are held Low
T2
Read Cycle
Memory Read/Write (with Wait State) Timing Diagram
TW
Read data
T3
T1
T2
Write Cycle
Write data
TW
T3