HYB18L256160B QIMONDA [Qimonda AG], HYB18L256160B Datasheet - Page 10

• Manufacturer Part Number: HYB18L256160B
• Description: DRAMs for Mobile Applications 256-Mbit Mobile-RAM
• Manufacturer: QIMONDA [Qimonda AG]

2.2.1.1
READ and WRITE accesses to the Mobile-RAM are burst oriented, with the burst length being programmable. The burst length
determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst
lengths of 1, 2, 4, 8 locations are available for both the sequential and interleaved burst types, and a full-page burst mode is
available for the sequential burst type.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses
for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is
uniquely selected by A1-A8 when the burst length is set to two, by A2-A8 when the burst length is set to four and by A3-A8
when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location
within the block.
Full page bursts wrap within the page if the boundary is reached. Please note that full page bursts do not self-terminate; this
implies that full-page read or write bursts with Auto Precharge are not legal commands.
Notes
1. For a burst length of 2, A1-Ai select the two-data-element block; A0 selects the first access within the block.
2. For a burst length of 4, A2-Ai select the four-data-element block; A0-A1 select the first access within the block.
3. For a burst length of 8, A3-Ai select the eight-data-element block; A0-A2 select the first access within the block.
4. For a full page burst, A0-Ai select the starting data element.
5. Whenever a boundary of the block is reached within a given sequence, the following access wraps within the block.
Rev. 1.73, 2006-09
01302004-CZ2R-J9SE
Burst Length
2
4
8
Full Page
A2
0
0
0
0
1
1
1
1
n
Starting Column Address
Burst Length
A1
0
0
1
1
0
0
1
1
0
0
1
1
n
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
n
Sequential
0 - 1 - 2 - 3
1 - 2 - 3 - 0
2 - 3 - 0 - 1
3 - 0 - 1 - 2
0 - 1 - 2 - 3 - 4 - 5 - 6 - 7
1 - 2 - 3 - 4 - 5 - 6 - 7 - 0
2 - 3 - 4 - 5 - 6 - 7 - 0 - 1
3 - 4 - 5 - 6 - 7 - 0 - 1 - 2
4 - 5 - 6 - 7 - 0 - 1 - 2 - 3
5 - 6 - 7 - 0 - 1 - 2 - 3 - 4
6 - 7 - 0 - 1 - 2 - 3 - 4 - 5
7 - 0 - 1 - 2 - 3 - 4 - 5 - 6
0 - 1
1 - 0
Cn, Cn+1, Cn+2, …
10
Order of Accesses Within a Burst
Interleaved
0 - 1
1 - 0
0 - 1 - 2 - 3
1 - 0 - 3 - 2
2 - 3 - 0 - 1
3 - 2 - 1 - 0
0 - 1 - 2 - 3 - 4 - 5 - 6 - 7
1 - 0 - 3 - 2 - 5 - 4 - 7 - 6
2 - 3 - 0 - 1 - 6 - 7 - 4 - 5
3 - 2 - 1 - 0 - 7 - 6 - 5 - 4
4 - 5 - 6 - 7 - 0 - 1 - 2 - 3
5 - 4 - 7 - 6 - 1 - 0 - 3 - 2
6 - 7 - 4 - 5 - 2 - 3 - 0 - 1
7 - 6 - 5 - 4 - 3 - 2 - 1 - 0
not supported
HY[B/E]18L256160B[C/F]L-7.5
256-Mbit Mobile-RAM
Burst Definition
TABLE 6
Data Sheet