HYB18L256160B QIMONDA [Qimonda AG], HYB18L256160B Datasheet - Page 6

• Manufacturer Part Number: HYB18L256160B
• Description: DRAMs for Mobile Applications 256-Mbit Mobile-RAM
• Manufacturer: QIMONDA [Qimonda AG]

1.4
Rev. 1.73, 2006-09
01302004-CZ2R-J9SE
Ball
CLK
CKE
CS
RAS, CAS,
WE
DQ0 - DQ15
LDQM,
UDQM
BA0, BA1
A0 - A12
V
V
V
V
N.C.
DDQ
SSQ
DD
SS
Type
Input
Input
Input
Input
I/O
Input
Input
Input
Supply
Supply
Supply
Supply
–
Pin Definition and Description
Detailed Function
Clock: all inputs are sampled on the positive edge of CLK.
Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals, device input
buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or
SUSPEND (access in progress). CKE is synchronous for POWER-DOWN entry and exit and for
SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit. Input buffers, excluding
CLK and CKE are disabled during power-down. Input buffers, excluding CKE are disabled during
SELF REFRESH.
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external
bank selection on systems with multiple memory banks. CS is considered part of the command
code.
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Data Inputs/Output: Bi-directional data bus (16 bit)
Input/Output Mask: input mask signal for WRITE cycles and output enable for READ cycles. For
WRITEs, DQM acts as a data mask when HIGH. For READs, DQM acts as an output enable and
places the output buffers in High-Z state when HIGH (two clocks latency).
LDQM corresponds to the data on DQ0 - DQ7; UDQM to the data on DQ8 - DQ15.
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVATE, READ, WRITE or
PRECHARGE command is being applied. BA0, BA1 also determine which mode register is to be
loaded during a MODE REGISTER SET command (MRS or EMRS).
Address Inputs: A0 - A12 define the row address during an ACTIVE command cycle. A0 - A8
define the column address during a READ or WRITE command cycle. In addition, A10 (= AP)
controls Auto Precharge operation at the end of the burst read or write cycle. During a
PRECHARGE command, A10 (= AP) in conjunction with BA0, BA1 controls which bank(s) are to
be precharged: if A10 is HIGH, all four banks will be precharged regardless of the state of BA0 and
BA1; if A10 is LOW, BA0, BA1 define the bank to be precharged. During MODE REGISTER SET
commands, the address inputs hold the op-code to be loaded.
I/O Power Supply: Isolated power for DQ output buffers for improved noise immunity:
to 1.95V
I/O Ground
Power Supply: Power for the core logic and input buffers,
Ground
No Connect
6
V
DD
= 1.65V to 1.95V
HY[B/E]18L256160B[C/F]L-7.5
256-Mbit Mobile-RAM
Pin Description
TABLE 4
V
DDQ
Data Sheet
= 1.65V