HYB18L256160B QIMONDA [Qimonda AG], HYB18L256160B Datasheet - Page 12

• Manufacturer Part Number: HYB18L256160B
• Description: DRAMs for Mobile Applications 256-Mbit Mobile-RAM
• Manufacturer: QIMONDA [Qimonda AG]

2.2.1.6
Partial Array Self Refresh is a power-saving feature specific to Mobile RAMs. With PASR, self refresh may be restricted to
variable portions of the total array. The selection comprises all four banks (default), two banks, one bank, half of one bank, and
a quarter of one bank. Data written to the non activated memory sections will get lost after a period defined by
(cf.
2.2.1.7
DRAM devices store data as electrical charge in tiny capacitors that require a periodic refresh in order to retain the stored
information. This refresh requirement heavily depends on the die temperature: high temperatures correspond to short refresh
periods, and low temperatures correspond to long refresh periods.
The Mobile-RAM is equipped with an on-chip temperature sensor which continuously senses the actual die temperature and
adjusts the refresh period in Self Refresh mode accordingly. This makes any programming of the TCSR bits in the Extended
Mode Register obsolete. It also is the superior solution in terms of compatibility and power-saving, because
• it is fully compatible to all processors that do not support the Extended Mode Register
• it is fully compatible to all applications that only write a default (worst case) TCSR value, e.g. because of the lack of an
• it does not require any processor interaction for regular TCSR updates
2.2.1.8
The drive strength of the DQ output buffers is selectable via bits A5 and A6 and shall be set load dependent. The half drive
strength is suitable for typical Mobile-RAM applications. The full drive strength is intended for heavier loaded systems.
I
Rev. 1.73, 2006-09
01302004-CZ2R-J9SE
Field
TCSR
PASR
-
V
external temperature sensor
Table
curves for full drive strength and half drive strength can be found in
15).
Bits
[4:3]
[2:0]
Partial Array Self Refresh (PASR)
Temperature Compensated Self Refresh (TCSR)
Selectable Drive Strength
Type
w
w
Description
Temperature Compensated Self Refresh
XX
Partial Array Self Refresh
000
001
010
101
110
Note: All other bit combinations are RESERVED.
B
B
B
B
B
B
Superseded by on-chip temperature sensor (see text)
all banks (default)
1/2 array (BA1 = 0)
1/4 array (BA1 = BA0 = 0)
1/8 array (BA1 = BA0 = RA12 = 0)
1/16 array (BA1 = BA0 = RA12 = RA11 = 0)
12
Table
29.
HY[B/E]18L256160B[C/F]L-7.5
256-Mbit Mobile-RAM
Data Sheet
t
REF