HYB18L256160B QIMONDA [Qimonda AG], HYB18L256160B Datasheet - Page 50

• Manufacturer Part Number: HYB18L256160B
• Description: DRAMs for Mobile Applications 256-Mbit Mobile-RAM
• Manufacturer: QIMONDA [Qimonda AG]

1) 0 °C ≤
2) All parameters assumes proper device initialization.
3) AC timing tests measured at 0.9 V.
4) The transition time
5) Specified
6) If
7) If
8) These parameter account for the number of clock cycles and depend on the operating frequency, as follows:
9) The write recovery time of
Rev. 1.73, 2006-09
01302004-CZ2R-J9SE
Parameter
DQM write mask latency
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE bank A to ACTIVE bank B delay
ACTIVE to PRECHARGE command period
WRITE recovery time
PRECHARGE command period
Refresh period (8192 rows)
Self refresh exit time
no. of clock cycles = specified delay / clock period; round up to next integer.
two clock cycles for
applications.
t
t
T
T
(CLK) > 1 ns, a value of (
> 1 ns, a value of (
T
C
t
≤ 70 °C (comm.); -25 °C ≤
AC
and
t
OH
t
T
t
WR
is measured between
parameters are measured with a 30 pF capacity load only as shown in
t
T
are mandatory. Qimonda Technologies recommends to use two clock cycles for the write recovery time in all
- 1) ns has to be added to this parameter.
t
WR
t
T
= 14 ns allows the use of one clock cycle for the write recovery time when
/2 - 0.5) ns has to be added to this parameter.
T
C
≤ 85 °C (ext.);
V
IH
and
V
IL
V
; all AC characteristics assume
DD
=
I/O
V
DDQ
50
= 1.65V to 1.95V;
t
t
t
t
t
t
t
t
t
DQW
RC
RCD
RRD
RAS
WR
RP
REF
SREX
Symbol
30 pF
0
67
19
15
45
14
19
—
1
Measurement Conditions for t
min.
t
T
= 1 ns.
Figure
- 7.5
—
—
—
—
100k
—
—
64
—
HY[B/E]18L256160B[C/F]L-7.5
max.
47.
f
CK
≤ 72 MHz. With
256-Mbit Mobile-RAM
t
ns
ns
ns
ns
ns
ns
ms
t
CK
CK
Unit
FIGURE 47
—
8)
8)
8)
8)
9)
8)
—
—
Note
Data Sheet
AC
f
CK
and t
> 72 MHz
1)2)3)4)
OH