HYB18L256160B QIMONDA [Qimonda AG], HYB18L256160B Datasheet - Page 14

• Manufacturer Part Number: HYB18L256160B
• Description: DRAMs for Mobile Applications 256-Mbit Mobile-RAM
• Manufacturer: QIMONDA [Qimonda AG]

2.4
1) DESELECT and NOP are functionally interchangeable.
2) BA0, BA1 provide bank address, and A0 - A12 provide row address.
3) BA0, BA1 provide bank address, A0 - A8 provide column address; A10 HIGH enables the Auto Precharge feature (non persistent), A10
4) This command is BURST TERMINATE if CKE is HIGH, DEEP POWER DOWN if CKE is LOW. The BURST TERMINATE command is
5) A10 LOW: BA0, BA1 determine which bank is precharged.
6) This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7) Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8) BA0, BA1 select either the Mode Register (BA0 = 0, BA1 = 0) or the Extended Mode Register (BA0 = 0, BA1 = 1); other combinations of
9) DQM LOW: data present on DQs is written to memory during write cycles; DQ output buffers are enabled during read cycles; DQM HIGH:
Address (A0 - A12, BA0, BA1), write data (DQ0 - DQ15) and command inputs (CKE, CS, RAS, CAS, WE, DQM) are all
registered on the positive edge of CLK.
operations.
Rev. 1.73, 2006-09
01302004-CZ2R-J9SE
Command
NOP
ACT
RD
WR
BST
PRE
ARF
MRS
–
–
LOW disables the Auto Precharge feature.
defined for READ or WRITE bursts with Auto Precharge disabled only.
A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.
BA0, BA1 are reserved; A0 - A12 provide the op-code to be written to the selected mode register.
data present on DQs are masked and thus not written to memory during write cycles;
DQ output buffers are placed in High-Z state (two clocks latency) during read cycles.
DESELECT
NO OPERATION
ACTIVE (Select bank and row)
READ (Select bank and column and start read burst)
WRITE (Select bank and column and start write burst)
BURST TERMINATE or
DEEP POWER DOWN
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or
SELF REFRESH (enter self refresh mode)
MODE REGISTER SET
Data Write / Output Enable
Write Mask / Output Disable (High-Z)
Commands
Figure 5
shows the basic timing parameters, which apply to all commands and
14
H
L
L
L
L
L
L
L
L
–
–
CS RAS CAS WE DQM
X
H
L
H
H
H
L
L
L
–
–
X
H
H
L
L
H
H
L
L
–
–
X
H
H
H
L
L
L
H
L
–
–
HY[B/E]18L256160B[C/F]L-7.5
X
X
X
L/H
X
X
X
H
L/H
X
L
Command Overview
256-Mbit Mobile-RAM
X
X
Bank / Row
Bank / Col
X
Code
X
Op-Code
–
–
Bank / Col
Address
TABLE 8
Data Sheet
1)
1)
2)
3)
3)
4)
5)
6)7)
8)
9)
9)
Note