Z8F082A28100KIT ZILOG [Zilog, Inc.], Z8F082A28100KIT Datasheet - Page 103

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Z8F082A28100KIT

Manufacturer Part Number
Z8F082A28100KIT
Description
Z8 Encore XP-R F08xA Series with eXtended Peripherals
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
Operation
PS024705-0405
Data Format
RXD
TXD
CTS
DE
System Bus
The UART always transmits and receives data in an 8-bit data format, least-significant bit
first. An even or odd parity bit can be added to the data stream. Each character begins with
an active
11 illustrates the asynchronous data format employed by the UART without parity and
with parity, respectively.
Parity Generator
Low Start
Transmit Data
Transmit Shift
Register
Register
Receive Shifter
Parity Checker
Receive Data
Register
Figure 9.UART Block Diagram
bit and ends with either 1 or 2 active High Stop bits. Figures 10 and
P R E L I M I N A R Y
Status Register
Transmitter Control
with Address Compare
Receiver Control
Control Registers
Z8 Encore! XP
Product Specification
Baud Rate
Generator
®
F08xA Seriess
UART
85

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