Z8F082A28100KIT ZILOG [Zilog, Inc.], Z8F082A28100KIT Datasheet - Page 88

• Manufacturer Part Number: Z8F082A28100KIT
• Description: Z8 Encore XP-R F08xA Series with eXtended Peripherals
• Manufacturer: ZILOG [Zilog, Inc.]

PS024705-0405
2. Write to the Timer High and Low Byte registers to set the starting count value. Writing
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.
4. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing
5. Configure the associated GPIO port pin for the Timer Input alternate function.
6. Write to the Timer Control register to enable the timer.
7. Assert the Timer Input signal to initiate the counting.
CAPTURE/COMPARE Mode
In CAPTURE/COMPARE mode, the timer begins counting on the first external Timer
Input transition. The acceptable transition (rising edge or falling edge) is set by the TPOL
bit in the Timer Control Register. The timer input is the system clock.
Every subsequent acceptable transition (after the first) of the Timer Input signal captures
the current count value. The Capture value is written to the Timer PWM High and Low
Byte Registers. When the Capture event occurs, an interrupt is generated, the count value
in the Timer High and Low Byte registers is reset to
INPCAP
capture event.
If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the
Timer Reload High and Low Byte registers. Upon reaching the Compare value, the timer
generates an interrupt, the count value in the Timer High and Low Byte registers is reset to
0001H
the timer interrupt is not because of an input capture event.
The steps for configuring a timer for CAPTURE/COMPARE mode and initiating the
count are as follows:
1. Write to the Timer Control register to:
2. Write to the Timer High and Low Byte registers to set the starting count value
3. Write to the Timer Reload High and Low Byte registers to set the Compare value.
these registers only affects the first pass in GATED mode. After the first timer reset in
GATED mode, counting always begins at the reset value of
to the relevant interrupt registers. By default, the timer interrupt is generated for both
input deassertion and reload events. If appropriate, configure the timer interrupt to be
generated only at the input deassertion event or the reload event by setting TICONFIG
field of the TxCTL1 register.
–
–
–
–
(typically
and counting resumes. The
Disable the timer
Configure the timer for CAPTURE/COMPARE mode.
Set the prescale value.
Set the Capture edge (rising or falling) for the Timer Input.
bit in TxCTL1 register is set to indicate the timer interrupt is caused by an input
0001H
).
P R E L I M I N A R Y
INPCAP
bit in TxCTL1 register is cleared to indicate
0001H
Z8 Encore! XP
, and counting resumes. The
0001H
Product Specification
.
®
F08xA Series
Timers
70