Z8F082A28100KIT ZILOG [Zilog, Inc.], Z8F082A28100KIT Datasheet - Page 168
Z8F082A28100KIT
Manufacturer Part Number
Z8F082A28100KIT
Description
Z8 Encore XP-R F08xA Series with eXtended Peripherals
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
1.Z8F082A28100KIT.pdf
(244 pages)
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PS024705-0405
DEBUG Mode
Figure 23.Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (2)
The operating characteristics of the devices in DEBUG mode are:
•
•
•
•
•
Entering DEBUG Mode
•
•
Exiting DEBUG Mode
The device exits DEBUG mode following any of these operations:
•
•
•
•
RS-232 TX
RS-232 RX
The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to execute
specific instructions
The system clock operates unless in STOP mode
All enabled on-chip peripherals operate unless in STOP mode
Automatically exits HALT mode
Constantly refreshes the Watch-Dog Timer, if enabled
The device enters DEBUG mode after the eZ8 CPU executes a BRK (Breakpoint) instruc-
tion.
If the DBG pin is held Low during the most recent clock cycle of system reset, the part
enters DEBUG mode upon exiting system reset.
Clearing the DBGMODE bit in the OCD Control Register to 0.
Power-on reset
Voltage Brown-Out reset
Watch-Dog Timer reset
Transceiver
RS-232
P R E L I M I N A R Y
Open-Drain
Buffer
VDD
Z8 Encore! XP
10KOhm
DBG Pin
Product Specification
®
On-Chip Debugger
F08xA Series
150
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