Z8F082A28100KIT ZILOG [Zilog, Inc.], Z8F082A28100KIT Datasheet - Page 15
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Z8F082A28100KIT
Manufacturer Part Number
Z8F082A28100KIT
Description
Z8 Encore XP-R F08xA Series with eXtended Peripherals
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
1.Z8F082A28100KIT.pdf
(244 pages)
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®
Z8 Encore! XP
F08xA Series
Product Specification
xv
Table 28. Port A–D Output Data Register (PxOUT). . . . . . . . . . . . . . . . . . . . . . 43
Table 29. LED Drive Enable (LEDEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 30. LED Drive Level High Register (LEDLVLH) . . . . . . . . . . . . . . . . . . . . 44
Table 31. LED Drive Level Low Register (LEDLVLL). . . . . . . . . . . . . . . . . . . . . 45
Table 32. Trap and Interrupt Vectors in Order of Priority . . . . . . . . . . . . . . . . . . 47
Table 33. Interrupt Request 0 Register (IRQ0) . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 34. Interrupt Request 1 Register (IRQ1) . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 35. Interrupt Request 2 Register (IRQ2) . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 36. IRQ0 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 37. IRQ0 Enable High Bit Register (IRQ0ENH) . . . . . . . . . . . . . . . . . . . . 53
Table 38. IRQ0 Enable Low Bit Register (IRQ0ENL). . . . . . . . . . . . . . . . . . . . . 53
Table 39. IRQ1 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 40. IRQ1 Enable High Bit Register (IRQ1ENH) . . . . . . . . . . . . . . . . . . . . 54
Table 41. IRQ1 Enable Low Bit Register (IRQ1ENL). . . . . . . . . . . . . . . . . . . . . 55
Table 42. IRQ2 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 43. IRQ2 Enable High Bit Register (IRQ2ENH) . . . . . . . . . . . . . . . . . . . . 55
Table 44. IRQ2 Enable Low Bit Register (IRQ2ENL). . . . . . . . . . . . . . . . . . . . . 56
Table 45. Interrupt Edge Select Register (IRQES). . . . . . . . . . . . . . . . . . . . . . . 56
Table 46. Shared Interrupt Select Register (IRQSS) . . . . . . . . . . . . . . . . . . . . . 57
Table 47. Interrupt Control Register (IRQCTL) . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 48. Timer 0–1 High Byte Register (TxH) . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 49. Timer 0–1 Low Byte Register (TxL) . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 50. Timer 0–1 Reload High Byte Register (TxRH) . . . . . . . . . . . . . . . . . . 73
Table 51. Timer 0–1 Reload Low Byte Register (TxRL). . . . . . . . . . . . . . . . . . . 73
Table 52. Timer 0–1 PWM High Byte Register (TxPWMH) . . . . . . . . . . . . . . . . 73
Table 53. Timer 0–1 Control Register 0 (TxCTL0) . . . . . . . . . . . . . . . . . . . . . . . 74
Table 54. Timer 0–1 PWM Low Byte Register (TxPWML) . . . . . . . . . . . . . . . . . 74
Table 55. Timer 0–1 Control Register 1 (TxCTL1) . . . . . . . . . . . . . . . . . . . . . . . 75
Table 56. Watch-Dog Timer Approximate Time-Out Delays . . . . . . . . . . . . . . . 80
Table 57. Watch-Dog Timer Control Register (WDTCTL) . . . . . . . . . . . . . . . . . 82
PS024705-0405
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