Z8F082A28100KIT ZILOG [Zilog, Inc.], Z8F082A28100KIT Datasheet - Page 47

• Manufacturer Part Number: Z8F082A28100KIT
• Description: Z8 Encore XP-R F08xA Series with eXtended Peripherals
• Manufacturer: ZILOG [Zilog, Inc.]

HALT Mode
Peripheral-Level Power Control
Power Control Register Definitions
PS024705-0405
Power Control Register 0
Executing the eZ8 CPU’s HALT instruction places the device into HALT mode. In HALT
mode, the operating characteristics are:
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The eZ8 CPU can be brought out of HALT mode by any of the following operations:
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To minimize current in HALT mode, all GPIO pins that are configured as inputs must be
driven to one of the supply rails (V
In addition to the STOP and Halt modes, it is possible to disable each peripheral on each
of the Z8 Encore! XP
power consumption.
Each bit of the following registers disables a peripheral block, either by gating its system
clock input or by removing power from the block.
The default state of the transimpedance amplifier is OFF. To use the transimpedance
amplifier, clear the TRAM bit, turning it ON. Clearing this bit might interfere with normal
Primary oscillator is enabled and continues to operate
System clock is enabled and continues to operate
eZ8 CPU is stopped
Program counter (PC) stops incrementing
Watch-Dog Timer’s internal RC oscillator continues to operate
If enabled, the Watch-Dog Timer continues to operate
All other on-chip peripherals continue to operate
Interrupt
Watch-Dog Timer time-out (interrupt or reset)
Power-on reset
Voltage-brown out reset
External RESET pin assertion
®
F08xA Series devices. Disabling a given peripheral minimizes its
P R E L I M I N A R Y
CC
or GND).
Z8 Encore! XP
Product Specification
®
Low-Power Modes
F08xA Series
29