Z8F082A28100KIT ZILOG [Zilog, Inc.], Z8F082A28100KIT Datasheet - Page 73

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Z8F082A28100KIT

Manufacturer Part Number
Z8F082A28100KIT
Description
Z8 Encore XP-R F08xA Series with eXtended Peripherals
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS024705-0405
IRQ2 Enable High and Low Bit Registers
PA7ENL
R/W
R/W
0
0
7
7
PA6CENH—Port A Bit[6] or Comparator Interrupt Request Enable Low Bit
PAxENL—Port A Bit[x] Interrupt Request Enable Low Bit
Table 41 describes the priority control for IRQ2. The IRQ2 Enable High and Low Bit reg-
isters (Tables 42 and 43) form a priority encoded enabling for interrupts in the Interrupt
Request 2 register. Priority is generated by setting bits in each register.
Reserved—Must be 0.
C3ENH—Port C3 Interrupt Request Enable High Bit
C2ENH—Port C2 Interrupt Request Enable High Bit
where x indicates the register bits from 0–7.
IRQ2ENH[x] IRQ2ENL[x] Priority
PA6CENL
Table 42. IRQ2 Enable High Bit Register (IRQ2ENH)
Table 40. IRQ1 Enable Low Bit Register (IRQ1ENL)
R/W
R/W
6
0
6
0
0
0
1
1
Table 41. IRQ2 Enable and Priority Encoding
Reserved
PA5ENL
R/W
R/W
5
0
5
0
0
1
0
1
P R E L I M I N A R Y
PA4ENL
R/W
R/W
0
0
4
Disabled
Level 1
Level 2
Level 3
4
FC5H
FC7H
PA3ENL
C3ENH
R/W
R/W
3
0
3
0
Description
Disabled
Low
Nominal
High
Z8 Encore! XP
PA2ENL
C2ENH
R/W
R/W
0
0
2
2
Product Specification
PA1ENL
C1ENH
R/W
R/W
1
0
1
0
®
Interrupt Controller
F08xA Series
PA0ENL
C0ENH
R/W
R/W
0
0
0
0
55

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