Z8F082A28100KIT ZILOG [Zilog, Inc.], Z8F082A28100KIT Datasheet - Page 129

• Manufacturer Part Number: Z8F082A28100KIT
• Description: Z8 Encore XP-R F08xA Series with eXtended Peripherals
• Manufacturer: ZILOG [Zilog, Inc.]

PS024705-0405
Caution:
Continuous Conversion
5. CEN remains 1 while the conversion is in progress. A single-shot conversion requires
6. When the conversion is complete, the ADC control logic performs the following
7. If the ADC remains idle for 160 consecutive system clock cycles, it is automatically
When configured for continuous conversion, the ADC continuously performs an analog-
to-digital conversion on the selected analog input. Each new data value over-writes the
previous value stored in the ADC Data registers. An interrupt is generated after each con-
version.
Follow these steps for setting up the ADC and initiating continuous conversion:
1. Enable the acceptable analog input by configuring the general-purpose I/O pins for
2. Write the
In CONTINUOUS mode, ADC updates are limited by the input signal bandwidth of the
ADC and the latency of the ADC and its digital filter. Step changes at the input are not
detected at the next output from the ADC. The response of the ADC (in all modes) is
limited by the input signal bandwidth and the latency.
–
–
–
5129 system clock cycles to complete. If a single-shot conversion is requested from an
ADC powered-down state, the ADC uses 40 additional clock cycles to power-up
before beginning the 5129 cycle conversion.
operations:
–
–
–
–
–
powered-down.
alternate function. This action disables the digital input and output driver.
function is required.
If the internal voltage reference must be output to a pin, set the
The internal voltage reference must be enabled in this case.
Write the REFSELL bit of the pair {
voltage reference level or to disable the internal reference. The REFSELL bit is
contained in the
Set CEN to 1 to start the conversion.
11-bit two’s-complement result written to {ADCD_H[7:0], ADCD_L[7:5]}.
CEN resets to 0 to indicate the conversion is complete.
If the High and Low alarms are disabled, an interrupt request is sent to the
Interrupt Controller denoting conversion complete.
If the High alarm is enabled and the ADC value is higher than the alarm threshold,
an interrupt is generated.
If the Low alarm is enabled and the ADC value is lower than the alarm threshold,
an interrupt is generated.
ADC High Threshold Register
ADC Control Register 0
P R E L I M I N A R Y
and
REFSELH
.
ADC Low Threshold Register
,
Z8 Encore! XP
REFSELL
Product Specification
} to select the internal
Analog-to-Digital Converter
REFEXT
®
F08xA Series
if the alarm
bit to 1.
111