Z8F082A28100KIT ZILOG [Zilog, Inc.], Z8F082A28100KIT Datasheet - Page 133

• Manufacturer Part Number: Z8F082A28100KIT
• Description: Z8 Encore XP-R F08xA Series with eXtended Peripherals
• Manufacturer: ZILOG [Zilog, Inc.]

PS024705-0405
Caution:
Input Buffer Stage
Also note that in the second term, the multiplication should be performed before the divi-
sion by 2
Many applications require the measurement of an input voltage source with a high output
impedance. This ADC provides a buffered input for such situations. The drawback of the
buffered input is a limitation of the input range. When using unity gain buffered mode, the
input signal must be prevented from coming within 300mV of V
Very small input voltages (less than 300mV) may not be measured in BUFFERED mode.
This condition applies only to the input voltage level (with respect to ground) of each dif-
ferential input signal. The actual differential input voltage magnitude may be less than 300
mV.
The 20x gain mode has more complicated input signal requirements. Similar to the unity
gain buffered mode, both inputs must be prevented from coming within 300mV of either
supply. Because of the limitations in the output swing of the 20x gain stage, the following
additional constraints apply:
430 mV < 10 (V
430 mV < 10 (V
where
V
V
V
These differential mode limitations explain that the common mode voltage of the differen-
tial inputs must be significantly above ground and below the supply, and that the differen-
tial magnitude must exceed these limitations.
The input range of the unbuffered ADC swings from V
than 300mV must use the unbuffered input mode. If these signals do not contain low out-
put impedances, they might require off-chip buffering.
Signals outside the allowable input range can be used without instability or device dam-
age. Any ADC readings made outside the input range are subject to greater inaccuracy
than specified.
inp
inn
cm
Although the ADC can be used without the gain and offset compensation, it does exhibit
non-unity gain. Designing the ADC with sub-unity gain reduces noise across the ADC
range but requires the ADC results to be scaled by a factor of 8/7.
= (V
is the positive ADC input voltage,
is the negative ADC input voltage
16
inp
. Otherwise, the second term will incorrectly evaluate to zero.
- V
inn
inp
inn
)/2 (common mode voltage),
- V
- V
inn
inp
) + V
) + V
P R E L I M I N A R Y
cm
cm
< V
< V
DD
DD
- 430mV
- 430mV
Z8 Encore! XP
SS
to V
DD
Product Specification
SS
. Input signals smaller
Analog-to-Digital Converter
and 400mV of V
®
F08xA Series
DD
.
115