Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 154

• Manufacturer Part Number: Z8FMC04100
• Description: Z8 Encore-R Motor Control Flash MCUs
• Manufacturer: ZILOG [Zilog, Inc.]

132
Z8 Encore!
Product Specification
LIN-UART
RESET
FIELD
ADDR
BITS
R/W
®
RDA
Motor Control Flash MCUs
R
7
0
Table 69. LIN-UART Status 0 Register - LIN mode (U0STAT0)
nal to provide flow control in loopback mode. CTS only affects transmission if the CTSE
bit = 1.
Receive Data Available (RDA).
received data. Reading the Receive Data Register clears this bit.
Physical Layer Error (PLE).
match when a LIN slave or master is transmitting. This could be caused by a fault in the
physical layer or multiple devices driving the bus simultaneously. Reading the Status 0
Register or the Receive Data Register clears this bit.
Receive Data and Autobaud Overrun Error (OE).
operation if a receive data overrun error occurs. This bit is also set during LIN Slave auto-
baud if the BRG counter overflows before the end of the autobaud sequence, indicating
the receive activity was not an autobaud character or the master baud rate is too slow. The
ATB status bit will also be set in this case. This bit is cleared by reading the Receive Data
Register.
Framing Error (FE).
reception) was detected. Reading the Receive Data Register clears this bit.
Break Detect (BRKD).
least 4 bit times occurred (Wake-up event) or (b) in Slave Wait Break state and a break of
at least 11 bit times occurred (Break event) or (c) in Slave Active state and a break of at
least 10 bit times occurs. Reading the Status 0 Register or the Receive Data Register clears
this bit.
Transmitter Data Register Empty (TDRE).
Register is empty and ready for additional data. Writing to the Transmit Data Register
resets this bit.
Transmitter Empty (TXE).
character transmission is finished.
LIN Slave Autobaud Complete (ATB).
baud character is received. If the ABIEN bit is set in the LIN Control Register, then a
PLE
R
6
0
ABOE
This bit indicates that a framing error (no STOP bit following data
R
5
0
This bit is set in LIN mode if (a) in LinSleep state and a break of at
P R E L I M I N A R Y
This bit indicates that the transmit shift register is empty and
This bit indicates that transmit and receive data do not
This bit indicates that the Receive Data Register has
FE
R
4
0
F41H
This bit is set in LIN SLAVE mode when an auto-
BRKD
This bit indicates that the Transmit Data
R
3
0
This bit is set just as in normal UART
TDRE
R
2
1
TXE
R
1
1
PS024604-1005
ATB
R
0
0