Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 201

• Manufacturer Part Number: Z8FMC04100
• Description: Z8 Encore-R Motor Control Flash MCUs
• Manufacturer: ZILOG [Zilog, Inc.]

PS024604-1005
S
Slave Address
Figure 32. Data Transfer Format—Slave Receive Transaction with 7-Bit Address
1. The software configures the controller for operation as a slave in 7-bit addressing
2. The bus master initiates a transfer, sending the address byte. In SLAVE mode, the I
3. The software responds to the interrupt by reading the I2CISTAT Register (which
4. The master detects the Acknowledge and sends the byte of data.
5. The I
6. The software responds by reading the I2CISTAT Register, finding the
7. The master and slave loops through steps 4 to 6 until the master detects a Not
8. The master sends the
mode, as follows.
a. Initialize the
b. Optionally set the
c. Initialize the
d. Set
controller recognizes its own address and detects that the R/W bit = 0 (written from
the master to the slave). The I
accept the transaction. The
interrupt. The
slave. The I
the first data byte.
clears the
Because
If software is only able to accept a single byte it sets the
ter at this time.
Acknowledge depending on the state of the
controller generates the receive data interrupt by setting the
Register.
and reading the I2CDATA Register clearing the
one more data byte it sets the
Acknowledge instruction or runs out of data to send.
cause the I
Register). Because the slave received data from the master, the software takes no
action in response to the STOP interrupt other than reading the I2CISTAT Register to
clear the
or MASTER/SLAVE mode with 7-bit addressing.
2
C controller receives the data byte and responds with Acknowledge or Not
IEN
RD
STOP
SAM
2
W=0
2
C controller to assert a STOP interrupt (the
= 0, no immediate action is required until the first byte of data is received.
= 1 in the I
C controller holds the SCL signal Low, waiting for the software to load
RD
bit). After seeing the
bit in the I2CISTAT Register.
MODE
SLA[6:0]
bit in the I2CISTAT Register is cleared to 0, indicating a Write to the
STOP
A
GCE
field in the I
2
P R E L I M I N A R Y
C Control Register. Set
bit.
SAM
or
bits in the I
Data
2
NAK
RESTART
C controller acknowledges, indicating it is available to
bit in the I2CISTAT Register is set to 1, causing an
bit in the I2CCTL Register.
2
SAM
C Mode Register for either SLAVE ONLY mode
A
2
signal on the bus. Either of these signals can
bit to 1, the software checks the
C Slave Address Register.
NAK
Data
RDRF
NAK
bit in the I2CCTL Register. The I
= 0 in the I
bit. If software can accept only
A
STOP
NAK
RDRF
Product Specification
bit in the I2CCTL Regis-
bit = 1 in the I2CISTAT
Data
2
C Control Register.
bit in the I2CISTAT
Slave Transactions
RDRF
A/A
RD
bit = 1
bit.
P/S
2
2
C
C
179