Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 204

• Manufacturer Part Number: Z8FMC04100
• Description: Z8 Encore-R Motor Control Flash MCUs
• Manufacturer: ZILOG [Zilog, Inc.]

182
Z8 Encore!
Product Specification
I2C Master/Slave Controller
S Slave Address
1st Byte
Figure 35. Data Transfer Format—Slave Transmit Transaction with 10-Bit Address
®
Motor Control Flash MCUs
5. After the first bit of the first data byte has been transferred, the I
6. The software responds to the transmit data interrupt (
7. After the data byte has been received by the master, the master transmits an Acknowl-
8. The bus cycles through steps 5 to 7 until the final byte has been transferred. If the soft-
9. The software responds to the Not Acknowledge interrupt by clearing the
10. When the master has completed the final acknowledge cycle, it asserts a
11. The slave I
12. The software responds to the
Slave Transmit Transaction with 10-Bit Address
The data transfer format for a master reading data from a slave with 10-bit addressing is
shown in Figure 35. The following procedure describes the I
operating as a slave in 10-bit addressing mode, transmitting data to the bus master.
1. The software configures the controller for operation as a slave in 10-bit addressing
W = 0 A Slave Address
TDRE
data byte into the I2CDATA Register, which clears
edge instruction (or Not Acknowledge instruction if this byte is the final data byte).
ware has not yet loaded the next data byte when the master brings SCL Low to trans-
fer the most significant data bit, the slave I
register has been written. When a Not Acknowledge instruction is received by the
slave, the I
Acknowledge interrupt to be generated.
I2CCTL Register and by asserting the
data register.
RESTART
I2CISTAT Register).
ister, which clears the
mode.
a. Initialize the
b. Optionally set the
c. Initialize the
or MASTER/SLAVE mode with 10-bit addressing.
I2CMODE Register.
bit, which asserts the transmit data interrupt.
condition on the bus.
2
2
C controller sets the
C controller asserts the
2nd Byte
MODE
SLA[7:0]
SPRS
GCE
field in the I
P R E L I M I N A R Y
A
bit.
bit.
bits in the I2CSLVAD Register and
STOP/RESTART
S Slave Address
NCKI
2
STOP/RESTART
C Mode Register for either SLAVE ONLY mode
1st Byte
FLUSH
bit in the I2CISTAT Register, causing the Not
2
C controller holds SCL Low until the data
bit of the I2CCTL Register to empty the
interrupt by reading the I2CISTAT Reg-
R = 1 A Data A Data A
TDRE
interrupt (set
TDRE
2
.
C Master/Slave Controller
= 1) by loading the next
2
SLA[9:8]
C controller sets the
SPRS
PS024604-1005
TXI
bit in
STOP
in the
bit in the
or
P