Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 206

• Manufacturer Part Number: Z8FMC04100
• Description: Z8 Encore-R Motor Control Flash MCUs
• Manufacturer: ZILOG [Zilog, Inc.]

184
Z8 Encore!
Product Specification
I2C Master/Slave Controller
RESET
FIELD
ADDR
BITS
R/W
I
I
2
2
C Interrupt Status Register
®
C Data Register
Motor Control Flash MCUs
7
Table 92. I
12. The software responds to the
13. When the master has completed the Acknowledge cycle of the last transfer, it asserts a
14. The slave I
15. The software responds to the
The I
Shift Register to transmit onto the I
from the Shift Register after it is received from the I
accessible in the Register File address space, but is used only to buffer incoming and out-
going data.
Writes by the software to the I2CDATA Register are blocked if a slave Write transaction is
underway (the I
The read-only I
current I
one or more of the
RD
SAM
bits do not generate an interrupt but rather provide status associated with the
Register and by asserting the
STOP
I2CISTAT Register).
clearing the
bit interrupt.
2
C Data Register, shown in Table 92, contains the data that is to be loaded into the
2
C interrupt and provides status of the I
or
2
6
C Data Register (I2CDATA)
RESTART
2
2
2
C controller asserts the
SPRS
C Interrupt Status Register, shown in Table 93, indicates the cause of any
C controller is in SLAVE mode, and data is being received).
TDRE
bit.
condition on the bus.
5
,
RDRF
P R E L I M I N A R Y
,
NAK
FLUSH
STOP
SAM
2
4
C bus. This register also contains data that is loaded
interrupt by clearing the
,
STOP/RESTART
DATA
F50H
interrupt by reading the I2CISTAT Register and
ARBLST
R/W
bit of the I2CCTL Register.
0
2
3
,
C controller
SPRS
2
C bus. The I
or
interrupt (sets the
NCKI
2
. When an interrupt occurs,
TXI
bits is set. The
2
C Shift Register is not
bit in the I2CCTL
1
SPRS
PS024604-1005
GCA
bit in the
0
and