Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 255

• Manufacturer Part Number: Z8FMC04100
• Description: Z8 Encore-R Motor Control Flash MCUs
• Manufacturer: ZILOG [Zilog, Inc.]

* The reset value is 1 if the option bit LPDEN is 0.
PS024604-1005
RESET
FIELD
ADDR
BITS
R/W
Clock Failure Detection and Recovery for WDT Oscillator
Oscillator Control Register
INTEN
R/W
7
1
Table 130. Oscillator Control Register (OSCCTL)
Watch-Dog Timer oscillator to drive the system clock. Although this oscillator runs at a
much lower frequency than the original system clock, the CPU continues to operate,
allowing execution of a clock failure vector and software routines that either remedy the
oscillator failure or issue a failure alert. This automatic switch-over is not available if the
Watch-Dog Timer is the primary oscillator.
The primary oscillator failure detection circuitry asserts if the system clock frequency
drops below 1KHz ±+/-50%. For operating frequencies below 2KHz, do not enable the
clock failure circuitry (
In the event of a Watch-Dog Timer oscillator failure, a System Exception will be issued if
the
switch-over, but alerts the CPU of the failure. After a Watch-Dog Timer failure, it is no
longer possible to detect a primary oscillator failure.
The Watch-Dog Timer oscillator failure detection circuit counts system clocks while look-
ing for a Watch-Dog Timer clock. The logic counts 8000 system clock cycles before deter-
mining that a failure occurred. The system clock rate determines the speed at which the
Watch-Dog Timer failure can be detected. A very slow system clock results in very slow
detection times. If the Watch-Dog Timer is the primary oscillator or if the Watch-Dog
Timer oscillator is disabled, deassert the
The Oscillator Control Register (OSCCTL) enables/disables the various oscillator circuits,
enables/disables the failure detection/recovery circuitry, actively powers down the flash,
and selects the primary oscillator, which becomes the system clock.
The Oscillator Control Register must be unlocked before writing. Writing the two-step
sequence
register locks after completion of a register write to the OSCCTL.
WDFEN
XTLEN
E7H
R/W
bit of the OSCCTL register is set. This event does not trigger an attendant clock
6
0
followed by
WDTEN
R/W
POFEN
5
1
18H
P R E L I M I N A R Y Clock Failure Detection and Recovery for WDT
must be deasserted in the OSCCTL register).
to the Oscillator Control Register address unlocks it. The
POFEN
R/W
4
0
F86H
WDFEN
WDFEN
R/W
3
0
bit of the OSCCTL register.
Z8FMC16100 Series Flash MCU
FLPEN
R/W
0*
2
Product Specification
1
SCKSEL
R/W
00
0
233