Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 198

• Manufacturer Part Number: Z8FMC04100
• Description: Z8 Encore-R Motor Control Flash MCUs
• Manufacturer: ZILOG [Zilog, Inc.]

176
Z8 Encore!
Product Specification
I2C Master/Slave Controller
®
Motor Control Flash MCUs
3. The software asserts the
4. The I
5. The I
6. After the first bit has been shifted out, a transmit interrupt is asserted.
7. The software responds by writing the least significant eight bits of address to the I
8. The I
9. The I
10. The I
11. The I
12. The software responds by setting the
13. The software writes
14. If the user chooses to read only one byte, the software responds by setting the
15. After the I
16. The I
ister.
Data Register.
high period of SCL.
If the slave does not acknowledge the address byte, the I
bit in the I
Register. The software responds to the Not Acknowledge interrupt by setting the
bit and clearing the
sends the
tion is complete, and the following steps can be ignored.
ister (the lower byte of the 10-bit address).
the I
a repeated
I
of the I
transfer), the I
the next High period of SCL.
If the slave does not acknowledge the address byte, the I
bit in the I
Register. The software responds to the Not Acknowledge interrupt by setting the
bit and clearing the
sends the
tion is complete, and the following steps can be ignored.
2
C Data Register.
2
2
2
2
2
2
2
2
C controller generates a transmit interrupt.
C controller sends a
C controller loads the I
C controller completes shifting of the first address byte.
C slave sends an Acknowledge by pulling the SDA signal Low during the next
C controller loads the I
C controller shifts out the next eight bits of the address. After the first bit shifts,
C controller sends a repeated
2
C Control Register.
STOP
STOP
2
2
2
START
C Status Register, sets the
C controller shifts out the address bits listed in Step 9 (the second address
C Status Register, sets the
2
C slave sends an Acknowledge by pulling the SDA signal Low during
condition on the bus and clears the
condition on the bus, and clears the
condition.
TXI
TXI
11110b
P R E L I M I N A R Y
bit. The I
bit. The I
START
START
, followed by the 2-bit slave address and a 1 (Read) to the
2
2
C Shift Register with the contents of the I
C Shift Register with the contents of the I
bit of the I
2
2
condition.
C controller flushes the Transmit Data Register,
C controller flushes the Transmit Data Register,
START
START
ACKV
ACKV
2
condition.
C Control Register.
bit and clears the
bit, and clears the
bit of the I
STOP
STOP
2
C Control Register to generate
2
2
C controller sets the NCKI
and
C controller sets the NCKI
and
ACK
NCKI
ACK
NCKI
bit in the I
bit in the I
bits. The transac-
bits. The transac-
PS024604-1005
2
2
C Data Reg-
C Data Reg-
2
2
C State
NAK
C State
STOP
STOP
2
bit
C