Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 80

• Manufacturer Part Number: Z8FMC04100
• Description: Z8 Encore-R Motor Control Flash MCUs
• Manufacturer: ZILOG [Zilog, Inc.]

58
Z8 Encore!
Product Specification
Interrupt Controller
Bit
Position
[1]
PA51I
[0]
PA40I
RESET
FIELD
ADDR
BITS
R/W
IRQ0 Enable High and Low Bit Registers
PWMENH
®
Value
(H)
0
1
0
1
R/W
Motor Control Flash MCUs
7
0
Table 33. IRQ0 Enable High Bit Register (IRQ0ENH)
The IRQ0 Enable High and Low Bit registers, shown in Tables 33 and 34, form a priority
encoded enabling for interrupts in the Interrupt Request 0 Register. Priority is generated
by setting bits in each register. Table 32 describes the priority control for IRQ0.
Table 32. IRQ0 Enable and Priority Encoding
PWMENH—Pulse-Width Modulator Interrupt Request Enable High Bit
FLTENH—Fault Interrupt Request Enable High Bit
ADCENH—ADC Interrupt Request Enable High Bit
CMPENH—Comparator Interrupt Request Enable High Bit
IRQ0ENH[x] IRQ0ENL[x] Priority
Note: x indicates the register bits from 0 through 7.
0
0
1
1
FLTENH
Description
PA5 or PA1 Interrupt Request — Logic in the Port A GPIO module selects either
PA5 or PA1 and either rising or falling edge.
No interrupt request is pending for PA5 or PA1
An interrupt request from PA5 or PA1 is awaiting service.
PA4 or PA0 Interrupt Request — Logic in the Port A GPIO module selects either
PA4 or PA0 and either rising or falling edge.
No interrupt request is pending for PA4 or PA0
An interrupt request from PA4 or PA0 is awaiting service.
R/W
6
0
ADCENH CMPENH
0
1
0
1
R/W
5
0
P R E L I M I N A R Y
Disabled
Level 1
Level 2
Level 3
R/W
4
0
FC1H
T0ENH
R/W
Description
Disabled
Low
Nominal
High
3
0
U0RENH
R/W
2
0
U0TENH
R/W
1
0
PS024604-1005
SPIENH
R/W
0
0