Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 189

• Manufacturer Part Number: Z8FMC04100
• Description: Z8 Encore-R Motor Control Flash MCUs
• Manufacturer: ZILOG [Zilog, Inc.]

PS024604-1005
I
2
C Interrupts
The I
request signal to the interrupt controller. If the I
interrupt is determined by which bits are set in the I2CISTAT Register. If the I
ler is disabled, the BRG controller can be used to generate general-purpose timer inter-
rupts.
Each interrupt source, other than the baud rate generator interrupt, features an associated
bit in the I2CISTAT Register that clears automatically when software reads the register or
performs another task, such as reading/writing the data register.
Transmit Interrupts
Transmit interrupts (
of which must be true.
•
•
Writing to the I
Receive Interrupts
Receive interrupts (
received by the I
ister. If the RDRF interrupt is not serviced prior to the completion of the next Receive
byte, the I
RDRF
slave receives an address byte or for data bytes following a slave address that did not
match. An exception is if the Interactive Receive Mode (
Register, in which case Receive interrupts occur for all Receive address and data bytes in
SLAVE mode.
Slave Address Match Interrupts
Slave address match interrupts (
in SLAVE mode and an address is received that matches the unique slave address. The
General Call Address (
GCE
Register to determine if the transaction is a Read or Write transaction. The General Call
Address and STARTBYTE address are also distinguished by the
The transmit data register is empty and the
The I
–
–
–
bit = 1 in the I2CMODE Register. The software checks the
2
is cleared, to prevent receive overruns. A receive interrupt does not occur when a
C controller contains multiple interrupt sources that are combined into one interrupt
The first bit of a 10-bit address is shifted out
The first bit of the final byte of an address is shifted out and the
serted
The first bit of a data byte is shifted out
2
2
C controller is enabled, with one of the following:
C controller holds SCL Low during the final data bit of the next byte until
2
C Data Register always clears the
2
C controller. The
RDRF
TDRE
0000_0000
bit = 1 in I2CISTAT) occur when a byte of data has been
bit = 1 in I2CISTAT) occur under the following conditions, both
P R E L I M I N A R Y
SAM
) and STARTBYTE (
RDRF
bit = 1 in I2CISTAT) occur when the I
bit is cleared by reading from the I
TXI
2
C controller is enabled, the source of the
TRDE
bit = 1 in the I
Z8FMC16100 Series Flash MCU
0000_0001
bit to 0.
IRM
) bit is set in the I2CMODE
RD
Product Specification
RD
2
C Control Register
bit in the I2CISTAT
) are recognized if the
bit. The General Call
RD
2
C controller is
bit is deas-
2
C Data Reg-
2
I
2
C control-
C Interrupts
167