Z8FMC04100 ZILOG [Zilog, Inc.], Z8FMC04100 Datasheet - Page 208

• Manufacturer Part Number: Z8FMC04100
• Description: Z8 Encore-R Motor Control Flash MCUs
• Manufacturer: ZILOG [Zilog, Inc.]

186
Z8 Encore!
Product Specification
NOTE: R/W1 - bit may be set (write 1) but not cleared.
I2C Master/Slave Controller
RESET
FIELD
ADDR
BITS
R/W
I
2
®
C Control Register
R/W
IEN
Motor Control Flash MCUs
7
0
Table 94. I
SPRS—Stop/Restart Condition Interrupt
This bit is set when the I
RESTART condition during a transaction directed to this slave. This bit clears when the
I2CISTAT register is read. Read the
whether the interrupt was caused by a STOP or RESTART condition.
NCKI—NAK Interrupt
In Master mode, this bit is set when a Not Acknowledge condition is received or sent and
neither the
by setting the
In Slave mode, this bit is set when a Not Acknowledge condition is received (Master read-
ing data from Slave), indicating the Master is finished reading. A STOP or RESTART con-
dition follows. In Slave mode this bit clears when the I2CISTAT register is read.
The I
IEN—I
This bit enables the I
START—Send Start Condition
When set, this bit causes the I
Start condition. Once asserted, it is cleared by the I
condition or by deasserting the
the bit. After this bit is set, the START condition is sent if there is data in the I2CDATA or
I2CSHIFT register. If there is no data in one of these registers, the I
until data is loaded. If this bit is set while the I
ates a RESTART condition after the byte shifts and the acknowledge phase completes. If
the
condition.
If START is set while a slave mode transaction is underway to this device, the START bit
will be cleared and ARBLST bit in the Interrupt Status register will be set.
STOP
2
C Control Register, shown in Table 94, enables and configures I
2
START
C Enable
R/W1
bit is also set, it also waits until the STOP condition is sent before the START
2
START
6
0
C Control Register (I2CCTL)
START
nor the
STOP
2
R/W1
or
C Controller.
5
0
STOP
2
C Controller is enabled in Slave mode and detects a STOP or
STOP
P R E L I M I N A R Y
2
bits.
C Controller (when configured as the Master) to send the
IEN
bit is active. In Master mode, this bit can only be cleared
BIRQ
R/W
4
0
bit. If this bit is 1, it cannot be cleared by writing to
RSTR
F52H
bit of the I2CSTATE register to determine
R/W
TXI
2
C Controller is shifting out data, it gener-
3
0
2
C Controller after it sends the Start
R/W1
NAK
2
0
2
C Controller waits
FLUSH
R/W
2
C operation.
1
0
PS024604-1005
FILTEN
R/W
0
0