S71GS128NB0 SPANSION [SPANSION], S71GS128NB0 Datasheet - Page 105

• Manufacturer Part Number: S71GS128NB0
• Description: 128N based MCPs
• Manufacturer: SPANSION [SPANSION]

Note: The CLK and ADV# inputs can be tied to V
WAIT will be asserted but should be ignored during asynchronous and page mode operations.
October 4, 2004 cellRAM_00_A0
128M: A[22:0]
64M: A[21:0]
32M: A[20:0]
DQ[15:0]
Symbol
ADV#
WAIT
WE#
V
V
CE#
OE#
UB#
CRE
LB#
CLK
V
V
CC
SS
CC
SS
Q
Q
Output
Output
Supply
Supply
Supply
Supply
Input/
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
A d v a n c e
Address Inputs: Inputs for addresses during READ and WRITE operations. Addresses are
internally latched during READ and WRITE cycles. The address lines are also used to define
the value to be loaded into the BCR or the RCR.
Clock: Synchronizes the memory to the system operating frequency during synchronous
operations. When configured for synchronous operation, the address is latched on the first
rising CLK edge when ADV# is active. CLK is static (HIGH or LOW) during asynchronous
access READ and WRITE operations and during PAGE READ ACCESS operations.
Address Valid: Indicates that a valid address is present on the address inputs. Addresses
can be latched on the rising edge of ADV# during asynchronous READ and WRITE
operations. ADV# can be held LOW during asynchronous READ and WRITE operations.
Configuration Register Enable: When CRE is HIGH, WRITE operations load the RCR or BCR.
Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and
goes into standby or deep power-down mode.
Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the output
buffers are disabled.
Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a
WRITE to either a configuration register or to the memory array.
Lower Byte Enable. DQ[7:0]
Upper Byte Enable. DQ[15:8]
Data Inputs/Outputs.
Wait: Provides data-valid feedback during burst READ and WRITE operations. The signal is
gated by CE#. WAIT is used to arbitrate collisions between refresh and READ/WRITE
operations. WAIT is asserted when a burst crosses a row boundary. WAIT is also used to
mask the delay associated with opening a new internal page. WAIT is asserted and should
be ignored during asynchronous and page mode operations. WAIT is High-Z when CE# is
HIGH.
Device Power Supply: (1.7V–1.95V) Power supply for device core operation.
I/O Power Supply: (1.7V–1.95V) Power supply for input/output buffers.
V
V
SS
SS
Q must be connected to ground.
must be connected to ground.
Table 15. Signal Descriptions
I n f o r m a t i o n
SS
CellularRAM Type 2
if the device is always operating in asynchronous or page mode.
Description
105