S71GS128NB0 SPANSION [SPANSION], S71GS128NB0 Datasheet - Page 169

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S71GS128NB0

Manufacturer Part Number
S71GS128NB0
Description
128N based MCPs
Manufacturer
SPANSION [SPANSION]
Datasheet
Note: CE# can stay LOW when transitioning between asynchronous operations. If CE# goes HIGH, it must remain HIGH
for at least 5ns (t
lularRAM™ Operation”
October 4, 2004 cellRAM_00_A0
DQ[15:0]
LB#/UB#
A[22:0]
Table 62. WRITE Timing Parameters—Asynchronous WRITE Followed by Asynchronous READ
ADV#
WAIT
Symbol
WE#
OE#
CE#
t
t
t
t
t
t
t
t
t
AVH
AVS
CVS
AW
BW
CW
DW
DH
AS
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V OH
V OL
V IH
V IL
CBPH
t VPH t VP
High-Z
) to schedule the appropriate internal refresh operation. See
Figure 60. Asynchronous WRITE Followed by Asynchronous READ
for restrictions on the maximum CE# LOW time (t
t AVS
t WHZ
t CVS
t AS
Address
t CW
Valid
Min
A d v a n c e
10
70
70
10
70
23
t WP t WPH
0
5
0
t AVH
DATA
t DH
70ns/80 MHz
t WC
t AW
t VS
t BW
Address
DATA
t AS
t DW
Valid
t WR
I n f o r m a t i o n
Max
CellularRAM Type 2
(Note)
t CBPH
V OH
V OL
Min
10
85
85
10
85
23
0
5
0
High-Z
t BLZ
CEM
85ns/66 MHz
).
t AA
t LZ
t CEM
Address
Valid
Legend:
“How Extended Timings Impact Cel-
Max
t OE
t OLZ
Don't Care
Output
Valid
t HZ
t BHZ
t OHZ
Units
Undefined
ns
ns
ns
ns
ns
ns
ns
ns
ns
169

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