S71GS128NB0 SPANSION [SPANSION], S71GS128NB0 Datasheet - Page 129

• Manufacturer Part Number: S71GS128NB0
• Description: 128N based MCPs
• Manufacturer: SPANSION [SPANSION]

Notes:
1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
2. See
3. High-Z to Low-Z timings are tested with the circuit shown in
4. 100mV transition away from the High-Z (V
5. Low-Z to High-Z timings are tested with the circuit shown in
October 4, 2004 cellRAM_00_A0
CE# HIGH between Subsequent Mixed-Mode Operations
transition from either V
“How Extended Timings Impact CellularRAM™ Operation”
Chip Disable to DQ and WAIT High-Z Output
LB#/UB# Disable to DQ High-Z Output
Output Disable to DQ High-Z Output
Output Hold from Address Change
LB#/UB# Enable to Low-Z Output
Output Enable to Low-Z Output
Address Hold from ADV# HIGH
Address Setup to ADV# HIGH
Output Enable to Valid Output
Chip Enable to Low-Z Output
Maximum CE# Pulse Width
CE# LOW to ADV# HIGH
Chip Select Access Time
ADV# Pulse Width HIGH
CE# LOW to WAIT Valid
ADV# Pulse Width LOW
LB#/UB# Access Time
Address Access Time
ADV# Access Time
Page Access Time
READ Cycle Time
Page Cycle Time
Parameter
Table 31. Asynchronous READ Cycle Timing Requirements
OH
A d v a n c e
or V
OL
toward V
CC
I n f o r m a t i o n
CC
Q/2.
Q/2) level toward either V
CellularRAM Type 2
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
AADV
CBPH
t
t
t
t
CEW
t
t
t
t
t
AVH
BHZ
CEM
t
OHZ
APA
AVS
BLZ
CVS
OLZ
VPH
OH
AA
BA
CO
HZ
OE
RC
LZ
PC
VP
Figure
Figure
below.
38. The Low-Z timings measure a
38. The High-Z timings measure a 100mV
Min
85ns/66 MHz
10
10
10
10
25
85
10
10
5
5
1
5
5
OH
or V
Max
7.5
85
85
25
85
85
20
8
4
8
8
OL
.
Min
70ns/80 MHz
10
10
10
10
20
70
10
10
5
5
1
5
5
Max
7.5
70
70
20
70
70
20
8
4
8
8
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
4
3
2
4
3
4
3
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