S71GS128NB0 SPANSION [SPANSION], S71GS128NB0 Datasheet - Page 171

• Manufacturer Part Number: S71GS128NB0
• Description: 128N based MCPs
• Manufacturer: SPANSION [SPANSION]

October 4, 2004 cellRAM_00_A0
Page Mode Disabled
Page Mode Enabled
Asynchronous
Asynchronous
Page Mode
Asynchronous WRITE Operation
Burst
The timing parameters provided in
must be completed within 4µs. After completing a WRITE operation, the device
must either enter standby (by transitioning CE# HIGH), or else perform a second
operation (READ or WRITE) using a new address.
onstrate these constraints as they apply during an asynchronous (page-mode-
disabled) operation. Either the CE# active period (t
dress valid period (t
operation, otherwise, the extended WRITE timings must be used.
Extended WRITE Timing— Asynchronous WRITE Operation
Modified timings are required during extended WRITE operations (see
An extended WRITE operation requires that both the write pulse width (t
the data valid period (t
time (t
a refresh operation and a successful completion of the WRITE operation.
WC
Table 64. Extended Cycle Impact on READ and WRITE Cycles
(See
t
CEM
[MIN]). These increased timings ensure that time is available for both
A d v a n c e
Figure 61
t
> 4µs (See
CEM
Timing Constraint
(See
t
CEM
and t
Figure
ADDRESS
ADDRESS
Figure 61. Extended Timing for t
> 4µs
TM
Figure 62. Extended Timing for t
and
TM
DW
Figure
in
> 4µs
CE#
CE#
61.)
Figure
) be lengthened to at least the minimum WRITE cycle
Figure
I n f o r m a t i o n
61.)
CellularRAM Type 2
62.)
62) must be less than 4µs during any WRITE
Figure 33
access times are t
All following intrapage READ
t CEM
t
TM
<
<
4µs
Burst must cross a row boundary within 4µs.
No impact.
require that all WRITE operations
Read Cycle
4 µs
Figure 61
CEM
AA
CEM
(not t
in
TM
Figure
and
APA
).
Figure 62
61) or the ad-
Must use extended WRITE
Must use extended WRITE
Figure
WP
(See
(See
dem-
) and
63).
Write Cycle
timing.
timing.
Figure
Figure
62)
63)
171