S71GS128NB0 SPANSION [SPANSION], S71GS128NB0 Datasheet - Page 175
S71GS128NB0
Manufacturer Part Number
S71GS128NB0
Description
128N based MCPs
Manufacturer
SPANSION [SPANSION]
Datasheet
1.S71GS128NB0.pdf
(195 pages)
- Current page: 175 of 195
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Notes:
1. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When LB# only is in select mode, only
2. When the device is in standby mode, control inputs (WE#, OE#), address inputs, and data inputs/outputs are
3. When WE# is invoked, the OE# input is internally disabled and has no effect on the I/Os.
4. The device consumes active power in this mode whenever addresses are changed.
5. V
6. DPD is enabled when configuration register bit CR[4] is “0”; otherwise, PAR is enabled.
December 15, 2004 cellRAM_02_A0
Standby
Read
Write
Active
PAR
DPD
Load Configuration
Register
DQ[7:0] are affected. When UB# only is in the select mode, DQ[15:8] are affected.
internally isolated from any external influence.
IN
Symbol
V
= V
SS
Q
CC
Mode
or 0V; all device balls must be static (unswitched) in order to achieve minimum standby current.
Supply
Type
Partial Array Refresh
A d v a n c e
Deep Power-down
Active > Standby
Active > Standby
V
Table 66. Bus Operations—Asynchronous Mode
SS
Standby
Standby
Active
Power
Q must be connected to ground.
Table 65. Pin Descriptions (Continued)
I n f o r m a t i o n
CE#
CellularRAM-2A
H
H
H
L
L
L
L
WE#
X
H
H
X
X
L
L
OE#
X
X
H
X
X
X
L
Description
LB#/UB#
X
X
X
X
L
L
L
ZZ#
H
H
H
H
L
L
L
Data-Out
DQ[15:0]
Data-In
(Note
High-Z
High-Z
High-Z
High-Z
High-Z
1)
1, 3,
Notes
2,
1,
4,
6
6
5
4
5
4
175
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