S71GS128NB0 SPANSION [SPANSION], S71GS128NB0 Datasheet - Page 110

• Manufacturer Part Number: S71GS128NB0
• Description: 128N based MCPs
• Manufacturer: SPANSION [SPANSION]

A d v a n c e
I n f o r m a t i o n
CE#
OE#
WE#
ADDRESS
ADD[0]
ADD[1]
ADD[2]
ADD[3]
t AA
t APA
t APA
t APA
D[0]
D[1]
D[2]
D[3]
DATA
LB#/UB#
Don't Care
Figure 25. Page Mode READ Operation (ADV# LOW)
Burst Mode Operation
Burst mode operations enable high-speed synchronous READ and WRITE opera-
tions. Burst operations consist of a multi-clock sequence that must be performed
in an ordered fashion. After CE# goes LOW, the address to access is latched on
the rising edge of the next clock that ADV# is LOW. During this first clock rising
edge, WE# indicates whether the operation is going to be a READ (WE# = HIGH,
Figure
26) or WRITE (WE# = LOW,
Figure
27).
The size of a burst can be specified in the BCR either as a fixed length or contin-
uous. Fixed-length bursts consist of four, eight, or sixteen words. Continuous
bursts have the ability to start at a specified address and burst through the entire
memory.
The latency count stored in the BCR defines the number of clock cycles that
elapse before the initial data value is transferred between the processor and Cel-
lularRAM device.
The WAIT output asserts as soon as a burst is initiated, and de-asserts to indicate
when data is to be transferred into (or out of) the memory. WAIT will again be
asserted if the burst crosses a row boundary. Once the CellularRAM device has
restored the previous row's data and accessed the next row, WAIT will be deas-
serted and the burst can continue (see
Figure
47).
To access other devices on the same bus without the timing penalty of the initial
latency for a new burst, burst mode can be suspended. Bursts are suspended by
stopping CLK. CLK can be stopped HIGH or LOW. If another device will use the
data bus while the burst is suspended, OE# should be taken HIGH to disable the
CellularRAM outputs; otherwise, OE# can remain LOW. Note that the WAIT out-
put will continue to be active, and as a result no other devices should directly
share the WAIT connection to the controller. To continue the burst sequence, OE#
is taken LOW, then CLK is restarted after valid data is available on the bus.
See
“How Extended Timings Impact CellularRAM™ Operation”
for restrictions on
the maximum CE# LOW time during burst operations. If a burst suspension will
110
CellularRAM Type 2
cellRAM_00_A0 October 4, 2004