S71GS128NB0 SPANSION [SPANSION], S71GS128NB0 Datasheet - Page 143
S71GS128NB0
Manufacturer Part Number
S71GS128NB0
Description
128N based MCPs
Manufacturer
SPANSION [SPANSION]
Datasheet
1.S71GS128NB0.pdf
(195 pages)
- Current page: 143 of 195
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Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
October 4, 2004 cellRAM_00_A0
DQ[15:0]
LB#/UB#
A[22:0]
ADV#
WAIT
WE#
OE#
CE#
CLK
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V OH
V OL
V OH
V OL
READ Burst Identified
High-Z
Figure 45. Four-word Burst READ Operation (with LB#/UB#)
(WE# = HIGH)
t SP
Address
t CSP
t SP
t SP
t SP
A d v a n c e
Valid
t CEW
High-Z
t HD
t HD
t HD
t HD
t OLZ
I n f o r m a t i o n
t ACLK
CellularRAM Type 2
t BOE
t KHTL
t CLK
OUTPUT
VALID
t KOH
OUTPUT
VALID
Legend:
t KHTL
High-Z
t KHTL
Don't Care
OUTPUT
VALID
t HD
t KHTL
t OHZ
t HZ
t CBPH
Undefined
High-Z
143
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