S71GS128NB0 SPANSION [SPANSION], S71GS128NB0 Datasheet - Page 112

• Manufacturer Part Number: S71GS128NB0
• Description: 128N based MCPs
• Manufacturer: SPANSION [SPANSION]

112
Mixed-Mode Operation
WAIT Operation
The device can support a combination of synchronous READ and asynchronous
WRITE operations when the BCR is configured for synchronous operation. The
asynchronous WRITE operation requires that the clock (CLK) remain static (HIGH
or LOW) during the entire sequence. The ADV# signal can be used to latch the
target address, or it can remain LOW during the entire WRITE operation. CE# can
remain LOW when transitioning between mixed-mode operations with fixed la-
tency enabled. Note that the t
This time is required to ensure adequate refresh. Mixed-mode operation facili-
tates a seamless interface to legacy burst mode Flash memory controllers. See
Figure 55
The WAIT output on a CellularRAM device is typically connected to a shared, sys-
tem-level WAIT signal (see
the processor to coordinate transactions with multiple memories on the synchro-
nous bus.
Once a READ or WRITE operation has been initiated, WAIT goes active to indicate
that the CellularRAM device requires additional time before data can be trans-
ferred. For READ operations, WAIT will remain active until valid data is output
from the device. For WRITE operations, WAIT will indicate to the memory control-
ler when data will be accepted into the CellularRAM device. When WAIT
transitions to an inactive state, the data burst will progress on successive clock
edges.
CE# must remain asserted during WAIT cycles (WAIT asserted and WAIT config-
uration BCR[8] = 1). Bringing CE# HIGH during WAIT cycles may cause data
corruption. (Note that for BCR[8] = 0, the actual WAIT cycles end one cycle after
WAIT de-asserts, and for row boundary crossings, start one cycle after the WAIT
signal asserts.)
When using variable initial access latency (BCR[14] = 0), the WAIT output per-
forms an arbitration role for READ or WRITE operations launched while an on-chip
refresh is in progress. If a collision occurs, the WAIT pin is asserted for additional
clock cycles until the refresh has completed (see
the refresh operation has completed, the READ or WRITE operation will continue
normally.
WAIT is also asserted when a continuous READ or WRITE burst crosses the
boundary between 128-word rows. The WAIT assertion allows time for the new
row to be accessed, and permits any pending refresh operations to be performed.
WAIT will be asserted but should be ignored during asynchronous READ and
WRITE, and page READ operations.
for the “Asynchronous WRITE Followed by Burst READ” timing diagram.
Figure 28. Wired or WAIT Configuration
Processor
READY
Figure 28
A d v a n c e
CKA
CellularRAM Type 2
Device
Other
period is the same as a READ or WRITE cycle.
WAIT
CellularRAM
below). The shared WAIT signal is used by
WAIT
Device
I n f o r m a t i o n
Other
WAIT
Figure 29
External
Pull-Up/
Pull-Down
Resistor
and
Figure
30). When
cellRAM_00_A0 October 4, 2004