S71GS128NB0 SPANSION [SPANSION], S71GS128NB0 Datasheet - Page 113

• Manufacturer Part Number: S71GS128NB0
• Description: 128N based MCPs
• Manufacturer: SPANSION [SPANSION]

Note: Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
October 4, 2004 cellRAM_00_A0
LB#/UB#
DQ[15:0]
A[22:0]
LB#/UB# Operation
ADV#
WAIT
WE#
CE#
OE#
CLK
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V OH
V OL
V OH
V OL
The LB# enable and UB# enable signals support byte-wide data transfers. During
READ operations, the enabled byte(s) are driven onto the DQs. The DQs associ-
ated with a disabled byte are put into a High-Z state during a READ operation.
During WRITE operations, any disabled bytes will not be transferred to the RAM
array and the internal value will remain unchanged. During an asynchronous
WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#,
LB#, or UB#, whichever occurs first.
When both the LB# and UB# are disabled (HIGH) during an operation, the device
will disable the data bus from receiving or transmitting data. Although the device
will seem to be deselected, it remains in an active mode as long as CE# remains
LOW.
High-Z
Additional WAIT states inserted to allow refresh completion.
Address
A d v a n c e
Valid
Figure 29. Refresh Collision During READ Operation
I n f o r m a t i o n
CellularRAM Type 2
D[0]
Legend:
D[1]
Don't care
D[2]
D[3]
Undefined
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