S71GS128NB0 SPANSION [SPANSION], S71GS128NB0 Datasheet - Page 131

• Manufacturer Part Number: S71GS128NB0
• Description: 128N based MCPs
• Manufacturer: SPANSION [SPANSION]

Notes:
1. See
2. Low-Z to High-Z timings are tested with the circuit shown in
3. High-Z to Low-Z timings are tested with the circuit shown in
October 4, 2004 cellRAM_00_A0
CE# HIGH between Subsequent Mixed-Mode Operations
transition from either V
transition away from the High-Z (V
“How Extended Timings Impact CellularRAM™ Operation”
Async Address-to-Burst Transition Time
Address Hold from ADV# Going HIGH
Address and ADV# LOW Setup Time
Address Setup to ADV# Going HIGH
Chip Disable to WAIT High-Z Output
LB#/UB# Select to End of Write
ADV# Setup to End of WRITE
Address Valid to End of Write
Chip Enable to Low-Z Output
End WRITE to Low-Z Output
WRITE to DQ High-Z Output
Chip Enable to End of Write
Maximum CE# Pulse Width
Data Hold from Write Time
WRITE Pulse Width HIGH
CE# Low to ADV# HIGH
Data WRITE Setup Time
ADV# Pulse Width HIGH
CE# LOW to WAIT Valid
CE# LOW to WAIT Valid
WRITE Recovery Time
WRITE Pulse Width
ADV# Pulse Width
WRITE Cycle Time
Parameter
Parameter
Table 33. Asynchronous WRITE Cycle Timing Requirements
OH
A d v a n c e
or V
Table 34. Burst WRITE Cycle Timing Requirements
OL
toward V
CC
Q/2) level toward either V
CC
I n f o r m a t i o n
Q/2.
CellularRAM Type 2
Symbol
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
CBPH
t
t
t
t
t
t
t
t
t
WHZ
WPH
t
CEM
CEW
t
t
CEW
AVH
AVS
CKA
CVS
VPH
OW
AW
BW
CW
DW
WC
WP
WR
DH
HZ
AS
LZ
VP
VS
Figure
Figure
below.
OH
Min
Min
70ns/80 MHz
10
70
70
70
10
70
23
10
10
10
70
70
46
10
70ns/80 MHz
0
5
1
0
5
0
5
1
or V
38. The High-Z timings measure a 100mV
38. The Low-Z timings measure a 100mV
OL
.
Max
Max
7.5
7.5
4
8
8
Min
Min
10
85
85
85
10
85
23
10
10
10
85
85
55
10
85ns/66 MHz
85ns/66 MHz
0
5
1
0
5
0
5
1
Max
Max
7.5
7.5
ns
4
8
8
Units
Units
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Notes
1
1
3
3
2
1
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