S71GS128NB0 SPANSION [SPANSION], S71GS128NB0 Datasheet - Page 184

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S71GS128NB0

Manufacturer Part Number
S71GS128NB0
Description
128N based MCPs
Manufacturer
SPANSION [SPANSION]
Datasheet
Note:I
Notes:
1. These parameters are verified in device characterization and are not 100% tested.
AC Characteristics
Notes:
1. AC test inputs are driven at VCCQ for a logic 1 and VSS for a logic 0. Input timing begins at VCCQ/2, and output
Note: All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
184
Partially Array Refresh Current
timing ends at VCCQ/2. Input rise and fall times (10% to 90%) < 1.6ns.
Input/Output Capacitance (DQ)
Deep Power-down
PAR
Description
(MAX) values measured with TCR set to 85°C.
Input Capacitance
Description
Description
Input
V CC Q
V SS
Table 71. Partial Array Refresh Specifications and Conditions
V
1.8 V
V
CC
IN
Table 73. Capacitance Specifications and Conditions
V CC Q /2
Q
Figure 70. AC Input/Output Reference Waveform
= V
V
Table 72. Deep Power-Down Specifications
CC
IN
ZZ# = Low
T
Q or 0V; +25°C; ZZ# = LOW CR[4] = 0
= V
Conditions
CR[4] = 1
C
= +25ºC; f = 1 MHz; V
CC
Figure 71. Output Load Circuit
Table 74. Output Load Circuit
Q or 0V,
DUT
A d v a n c e
Conditions
Conditions
CellularRAM-2A
Symbol
I
PAR
30pF
Test Points
V CC Q
IN
Density
64 Mb
R1
R2
= 0V
I n f o r m a t i o n
Test Point
Symbol
C
C
Partition
IN
IO
Array
Full
3/4
1/2
1/4
0
Symbol
V CC Q/2
I
Min
ZZ
-
-
2.7 KΩ
R1/R2
Typ
Max
Typ
6
6
cellRAM_02_A0 December 15, 2004
Output
TBD
TBD
TBD
Max
100
50
Units
Max
pF
pF
10
Units
Units
Notes
µA
µA
1
1

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