VT8601 Via, VT8601 Datasheet - Page 102

• Manufacturer Part Number: VT8601
• Description: Slot-1 / Socket-370 PCI North Bridge
• Manufacturer: Via

Additional CRTC Extended Registers
CR51 – Bus Grant Termination Control ......................... RW
CR52 – Shared Frame Buffer Control ............................ RW
CR55 – PCI Retry Control ............................................... RW
CR56 – Display Pre-end Fetch Control ........................... RW
CR57 – Display Pre-end Fetch Parameter ...................... RW
Revision 1.3 September 8, 1999
7, 5
7-0
3-0
5-0
7-2
7-0
6
4
7
6
1
0
7HFKQRORJLHV ,QF
Bus Grant Termination Position
This regiester is active if CR52[6] = 1
Shared Frame Buffer (SFB)
Bus Grant Termination Position Control
Reserved
Bus Grant Low Pulse (MCLKs) ...........def = 0010b
PCI Retry in Memory Write Command
PCI Retry in Memory Read Command
Number of PCICLKs * 2 for STOP#....... def = 0Fh
Number of PCICLKs, multiplied by 2, for generating
STOP# during the first data phase
Reserved
Display Queue Pre-end Fetch
Display Queue Pre-end Fetch Parameter Bit-8
Used with CR57 ......................................... default = 0
Display Queue Pre-end Fetch Parameter Bit-8
Used with CR56[0] .....................................default n/a
:H &
:H &R R QQHFW
00 Disable ...................................................default
01 Enable SFB slave mode 1 (8ma I/O buffer)
10 Enable SFB master mode
11 Enable SFB slave mode 2 (16ma I/O buffer)
0
1
0
1
0
1
0
1
QQHFW
Disable ...................................................default
Enable
Disable ...................................................default
Enable
Disable ...................................................default
Enable
Disable ...................................................default
Enable
........................................ always reads 0
........................................ always reads 0
-96
CR5E – Capture / ZV Port Control ................................ RW
CR5F – Test Control ........................................................ RW
5-3
5-1
7
6
2
1
0
7
6
0
Capture Idle......................................................... RO
Capture Command Port
Reserved
PCI I/O Write Retry
PCI I/O Read Retry
Capture Interface
This bit is protected by SRE_New[7]
Internal Control Test Output
Capture Input Interrupt Polarity Select
Reserved
Stop DISPQ REQ Test
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Disable................................................... default
Enable new command port (2203-2200h)
Disable................................................... default
Enable
Disable................................................... default
Enable
Disable................................................... default
Enable
Normal................................................... default
Internal control signals are output to P15-0
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
Normal................................................... default
Test data is output to pixel bus P15-0
Normal................................................... default
Stop DISPQ REQ
GEREQ
GEBUSY
CMDIN
GEWAIT
CMATCH
KGECYC
WBMT
GERTRY
BLANKTV
WRSTY
WRSTU
WRSTV
WRST1
Y0EN
UEN
YUVEN
........................................ always reads 0
........................................ always reads 0
VT8601 Apollo ProMedia
VGA Extended Registers