VT8601 Via, VT8601 Datasheet - Page 61

• Manufacturer Part Number: VT8601
• Description: Slot-1 / Socket-370 PCI North Bridge
• Manufacturer: Via

Device 0 Bus 1 Header Registers - Graphics Accelerator
The Apollo ProMedia 2D / 3D Graphics Accelerator is fully
compliant with PCI bus interface protocol revision 2.2. The
controller implements slave functions of PCI to accept cycles
initiated by PCI masters targeted for its internal registers,
RAMDAC™, frame buffer, and/or BIOS. It will accept only
one data transaction for non-memory type transfers; however
burst read/write transfers for frame buffer accesses are also
implemented for performance enhancement. Bursting is
disabled when accessing memory mapped I/O. Data parity
will be generated for read cycles.
To support the PC AT architecture, palette snooping is
supported. There are two different palette snooping modes:
(1) snooping due to PCI retry, and (2) snooping due to master
abort.
automatically determine the correct snooping mode in a PCI
based system during power up. The ProMedia follows the
PCI 2.2 specification running at 33 MHz or lower system
clock frequencies. For packed pixel modes, if the first data
TRDY is not generated within 16 clocks, a retry will be
issued. During bursting, if successful data is not generated
within 8 clocks, a retry will also be issued.
The table below lists the commands implemented by the
ProMedia graphics controller PCI interface. Note that codes
not listed (0000 interrupt acknowledge, 0001 special cycle,
0100, 0101, 1000, 1001 reserved, and 1101 dual address
cycle) are not decoded and DEVSEL# is not generated. No
action takes place inside the chip for these codes.
Revision 1.3 September 8, 1999
Command Code Command
7HFKQRORJLHV ,QF
Table 6. Supported PCI Command Codes
Both modes are supported. The video BIOS will
:H &
0010
0011
0110
0111
1010
1011
1100
1110
1111
:H &R R QQHFW
QQHFW
I/O Read
I/O Write
Memory Read
Memory Write
Configuration Read
Configuration Write
Memory Read Multiple
(treated as simple memory read)
Memory Read Line
(treated as simple memory read)
Memory Write and Invalid
(treated as simple memory write)
-55
The PCI configuration space is fully implemented. Due to the
second memory base register, all I/O registers can be memory
mapped; which allows more than one graphics controller to be
installed within a system by mapping memory and I/O to
different locations.
All configuration registers are located in PCI configuration
space and should be programmed using PCI configuration
mechanism 1 through CF8 / CFC with bus number equal to
one and function number and device number equal to zero.
There are three memory base registers. The first defines the
memory base location for the graphics frame buffer. The
second defines the memory base for the memory mapped I/O
locations. The third defines the memory base for the second
video aperture. With this second aperture, graphics data and
video data can be sent to the ProMedia simultaneously.
The ProMedia supports the PCI Bus Master mode which can
send captured video data directly to system memory for
processing. The registers to control the PCI Bus Master are
defined in following sections (they are all in PCI configuration
space).
Offset 1-0 - Vendor ID (1023h) ......................................... RO
Offset 3-2 - Device ID (8500h) .......................................... RO
15-0 ID Code
15-0 ID Code
Device 0 Bus 1 Header Registers - Graphics Accelerator
................................ always reads 1023h
................................ always reads 8500h
VT8601 Apollo ProMedia